On Jun 3, 2005, at 3:39 PM, Jonathan Stone wrote:

> Back in the days of 4BSD on a VAX, processor IPLs were effectively a
> counter, not bitfields; so _all_ SPLs that mapped to distinct CPU
> prioities always implicitly masked all lower SPLs.

It's really dependent on what the platform supports.

VAX has "interrupt levels", and blocking IPL 4 blocks 3, 2, and 1  
also.  m68k works similarly.  SPARC does, too.

On i386, you don't have "interrupt levels" on the processor like you  
do on VAX and m68k, there is just one level at the CPU, for all  
intents and purposes (controlled by cli/sti).  You DO have an  
interrupt controller with individually maskable interrupt sources.   
ARM systems are similar.  While this affords a little more  
flexibility, it is also possible to emulate the notion of a level  
hierarchy, as with the CPUs mentioned above.

> Do we have any such code, these days?

All over the place.

-- thorpej