On Sun, May 29, 2005 at 02:25:00PM -0400, Nathan J. Williams wrote:
> 
> Are you sure? Looking at the PCI spec, I don't see anything that
> restricts the use of byte lane enables in configuration space, and
> some PCI host bridges explicitly document the connection between byte
> and word reads on the host side and sub-dword accesses on the PCI
> side.

Indeed, you absolutely need to be able to write the 16bit 'command' register
without modifying the adjacent 'status' register - which is a 'write 1's
to clear' animal.

Section 3.1.1 (bus operation chapter) of my rev 2.0 PCI spec explicitly
says that the byte enable lines can be used to do transfers smaller than
32 bits.

	David

-- 
David Laight: david@l8s.co.uk