Subject: Re: splx() optimization [was Re: SMP re-eetrancy in "bottom half"
To: YAMAMOTO Takashi <yamt@mwd.biglobe.ne.jp>
From: Stephan Uphoff <ups@tree.com>
List: tech-kern
Date: 05/29/2005 19:11:13 
On Sun, 2005-05-29 at 17:37, YAMAMOTO Takashi wrote:
> > @@ -403,6 +405,8 @@
> >  	movl	CPUVAR(ILEVEL),%r13d					;\
> >  	cmpl	%ebx,%r13d						;\
> >  	jae	10f			/* currently masked; hold it */	;\
> > +	testl	$((1<<LIR_IPI) | (1<<LIR_TIMER)), CPUVAR(IPENDING)      ;\
> > +	jnz	10f           /* Let IPI and TIMER run first */         ;\
> >  	incl	MY_COUNT+V_INTR		/* statistical info */		;\
> >  	incq	IS_EVCNT(%r14)						;\
> 
> how about:
> 
> 	testl	$(-(1 << (num + 1))), CPUVAR(IPENDING)
> 

Only the IPI and timer interrupt pending bits are ordered.
( Pending interrupts (except IPI,timer) are not currently scheduled in
priority order on lowering the interrupt level) 

Your proposed change may pick up pending bits of interrupts that are
currently masked. This could delay interrupt delivery.

Stephan