On Sun, May 29, 2005 at 02:25:00PM -0400, Nathan J. Williams wrote:
> > PCI doesn't have a config read or write for anything but 32-bit
> > quantities.
> Are you sure? Looking at the PCI spec, I don't see anything that
> restricts the use of byte lane enables in configuration space, and
> some PCI host bridges explicitly document the connection between byte
> and word reads on the host side and sub-dword accesses on the PCI
> side.

Hmm...  Well, I was thinking about implementations where addressing
sub-32-bit quantities won't work as the low-order two bits of the
register address are reserved and/or specify the configuration
cycle type.  Granted, this is an implementation detail.

Looking at the 2.2 spec on page 22 (in section 3.1.1. Command
Definition), "... AD[1::0] are 00.  During the address phase of
a configuration transaction, AD[7::2] address one of the 64 DWORD
registers (where byte enables address the byte(s) within each DWORD)
in Configuration Space of each device.

So if the byte enables are properly set by the sub-DWORD read in
on the CFGDATA register (in such an implementation), then sub-DWORD
transactions should work.

Now I'm wondering if I misremember the exception.  Or if the code
was trying to write AD[1::0] instead of reading an offset into the
data.

-allen

-- 
 Allen Briggs                     briggs@wasabisystems.com
 Wasabi Systems, Inc.             http://www.wasabisystems.com/