Subject: Re: SMP re-entrancy in kernel drivers/"bottom half?"
To: Jonathan Stone <jonathan@dsg.stanford.edu>
From: Kentaro A. Kurahone <kurahone@sigusr1.org>
List: tech-kern
Date: 02/24/2005 22:23:55
On Thu, Feb 24, 2005 at 01:38:09PM -0800, Jonathan Stone wrote:
[snip]
> However, currently-available 10GbE products don't offer much offload:
> At most, large-send offload (aka TSO), and interrupt mitigation. It is
> a true fact that a single CPU[*] cannot keep up with such a device,
> and that future single CPUs will not be that much faster than today's
> single CPUs. Thus, if we want to support the PCI_X limited bandwidth
> today's hardware can achieve, the *only* viable option is to transform
> the stack into a pipeline, in which different CPUs handle different
> stages of the pipeline.

Hmmm.  Aren't there other issues with TCP/IP in general that cause
scalability issues on the high end?  Namedly that unrealistically good
link quality is neccecary to grow the window sufficiently?  (Though
there are a number of proposed changes to address this.  RFC3649 and 3472
for instance).
 
> So desiging a TCP stack that can only ever get high throughput from
> TOE NICs strikes me as a losing proposition.
> 
> [*] With, I suppose, the possible exceptiohn of a Itanic with monster
> 9MB caches. But NetBSD doesn't run on such CPUs yet anyway.

IPoIB might be able to do it too.  I've seen IB saturate PCI-X before,
but since that was using RDMA, I guess it's kind of hard to compare.
(Plus, "You need to but a $827 dollar interface, and rediculously expensive
cables/switches to make TCP go fast" seems subpar to me.)

I was pondering picking up an Adaptec TOE NAC, but for $800, I'm not sure
if I can justify the costs for the curiocity factor.

-- 
Kentaro A. Kurahone
SIGUSR1 Research and Development