--- Jared Momose <jpmomose@hotmail.com> wrote:

> 
> >Can we emulate virtual to phys translations using
> s/w?
> >It will slow things down, but will still be usable.
> I
> >mean, assume that every address space resides in a
> >contiguous block of memory and use a translation
> >scheme that translates only base addresses.
> 
> I suppose you could "protect" all
> data/bss/heap/stack pages such that a 
> read/write to any address would invoke an exception.
> You could then apply a 
> segment offset to the address according to the
> process, load/store the value 
> into/from the register, increment the program
> counter past the load/store 

I believe I have the answer but didn't provide the
details. gcc -fPIC will generate position independent
code. On blackfin, P5 register contains the base addr
which is added to the desired addr when doing a memory
access(lw/sw). So, during any context switch -we just
change the contents of <P5>. It will have the effect
of having 1 distinct contiguous physical address space
for every process, as also a distinct phys addr range
for the kernel. 

Does this make sense?

> instruction, and continue. This would be VERY
> inefficient but would be kinda 
> cool to see working! :^)
> 
> Best regards,
> Jared Momose
> 
Not if the generated code is position independent.

regards
-kamal
 


=====
------------------------------------------------------------
Kamal R. Prasad
UNIX systems consultant 
kamalp@acm.org

In theory, there is no difference between theory and practice. In practice, there is:-).
------------------------------------------------------------


		
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