Subject: Re: SMP re-entrancy in kernel drivers/"bottom half?"
To: YAMAMOTO Takashi <yamt@mwd.biglobe.ne.jp>
From: Jonathan Stone <jonathan@dsg.stanford.edu>
List: tech-kern
Date: 02/23/2005 19:02:19
In message <1109210591.339363.1130.nullmailer@yamt.dyndns.org>,
YAMAMOTO Takashi writes:
>(assuming you meant cr3,)
i386 TLB/cache flush on context-switch, yes.
> our current code defer switching until it's needed.
I had thought so too, but Nathan Williams thought otherwise yesterday.
If you and he reach agreement that we defer when not needed, I'll
gladly take your word on it.