Subject: Re: Should Alpha PCI code manage latency timers?
To: None <firstname.lastname@example.org>
From: List Mail User <track@Plectere.com>
Date: 01/25/2005 17:30:54
>From email@example.com Tue Jan 25 16:59:34 2005
>Date: Wed, 26 Jan 2005 01:58:54 +0100
>From: Jachym Holecek <firstname.lastname@example.org>
>To: List Mail User <track@Plectere.com>
>Cc: email@example.com, port-alpha@NetBSD.org, tech-kern@NetBSD.org,
>Subject: Re: Should Alpha PCI code manage latency timers?
>Reply-To: Jachym Holecek <firstname.lastname@example.org>
>Content-Type: text/plain; charset=us-ascii
>X-Window-System: Not needed
>> Just an interesting side note: The implementers of Intel motherboards
>> with the 430NX (Neptune) chipset misinterpreted the recommended value of 32
>> (i.e. 0x20 hex) and actually defaulted to 50 (i.e. 0x32 hex) -- Just some
>> (very old) history. More OT: [...]
>> Jachym, do you also have (or can get) the BIOS Implementor's Guide?
>> It contains (or did) the recommended sequence for determining and
>> initializing the system specific fields.
>I can't find this one on the PCISIG site.
>> Also, are you checking for PCI 2.1 or 2.2 (the common cases) or 2.3 (which
>> I have yet to see an implementation of) or *really* PCI 3.0 (which
>> includes PCI-Express, hot plug and a host of other `new' things?
>> Note, most of the old Alphas are probably either version 1.1 or 1.2.
>I checked 2.2, 2.3, 3.0 (yes, real version Three) -- they all seem to agree
>on the topic.
> -- Jachym Holecek
Well, I think that your up-to-date information should clearly "trumps"
my (over a decade old) memory and ancient "pink-copy" manuals. You should try
to find the PCI BIOS Implementor's guide (it may no longer exist or be up to
date, but older versions should still exist). If you or an organization which
you represent is a member of the PCI-SIG, a phone call should either get an old
copy of it at least a pointer to a reference - my old "pink" copy is version
1.0, though I believe at one point I held in my hand a v1.2 of the same or a
similar document from the SIG (white cover, so it had *really* been published,
not just a pre-release version for committee members).
It has been also been over a decade since I was personally responsible
for the PCI interface portion of any chip. In fact for the last few chips
which I was involved in (not counting "huge" organizations like Intel, where
I never had anything but email contact with the people who handled the bus
interface), we purchased library cells from TSMC to handle all but a few of
the finer points of DMA which were specific to the functions on those chips.
Thanks again for taking the initiative to get the info you have,