Subject: Re: Getting "TLB IPI rendezvous failed..."
To: Frank van der Linden <email@example.com>
From: Stephan Uphoff <firstname.lastname@example.org>
Date: 01/24/2005 11:56:23
On Sat, 2005-01-22 at 13:22, Frank van der Linden wrote:
> On Sat, Jan 22, 2005 at 09:21:59AM -0500, Stephan Uphoff wrote:
> > Could you try the attached patch?
> > Please make sure that all your com devices show up.
> Hmm.. I see your line of thinking here: you think that all the com
> devices, establishing interrupts, will overflow into the IDT entry
> for IPIs?
Yes - overflows into the same priority class as the IDT entry for the
IPI. With late interrupt acknowledge to the lapic this could block the
> That shouldn't happen, since there are only four ioapic pins involved
> here, and each of them will take one IDT entry, so they should end
> up as 0xd0-0xd3.
Unless something else is wrong (or COMPAT_SVR4 block 0xd2) I agree.
> The patch is good though, idt_vec_alloc should not go higher than
> entry 0xdf.
> Zeroing out idt_allocmap isn't needed, since it's declared
Mhhh OK - but who is zeroing BSS?