> > How is CHIP_W1_BUS different from CHIP_W1_SYS? Both are pointing to same
> > address! Is it something like physical and virtual address if so which
> > one contains physical and which virtual, OR is it something else.
> It is somthing else. If you have a bus bridge it may map the address
> space of the bus into the addres space of the CPU with an offset. 
> So you have to do a translation of bus addresses from and to CPU
> addresses. CHIP_W1_BUS specifies the address range as seen on the
> expansion bus and CHIP_W1_SYS specifies the same address range as 
> seen from the CPU.
> 
OK, that was a nice example given. Now I want to add some more with
respect TX4927 processor PCI mapping, the files goes something like this:

First file: sys/arch/evbmips/rbtx4927/rbtx4927reg.h
---------------------------------------------------------------
#define RBTX4927_MASTERCLK      25000000

#define RTC_BASE                0x1c010000

#define LAN_BASE                0x1c020280

#define PCIMEM_BASE             0x08000000          /* 
#define PCIMEM_SIZE             0x08000000
#define PCIMEM_PCI_BASE         0x08000000

#define PCIIO_BASE              0x16000000
#define PCIIO_SIZE              0x01000000
#define PCIIO_PCI_BASE          0x00000000

#define PCI_DMA_PCIBASE         0x00000000UL
#define PCI_DMA_PHYSBASE        0x00000000UL
#define PCI_DMA_SIZE            (256 * 1024 * 1024)
---------------------------------------------------------------


Second file: sys/arch/evbmips/rbtx4927/rbtx4927_bus_mem.c
---------------------------------------------------------------

/*
 * Platform-specific PCI bus memory support for the MIPS Malta.
 */

#include <sys/param.h>

#include <machine/bus.h>

#include <evbmips/rbtx4927/rbtx4927reg.h>
#include <evbmips/rbtx4927/rbtx4927var.h>

#define CHIP            rbtx4927
#define CHIP_MEM        /* defined */

#define CHIP_BUS_LITTLE_ENDIAN

/* MEM region 1 */
#define CHIP_W1_BUS_START(v)    PCIMEM_PCI_BASE
#define CHIP_W1_BUS_END(v)      (PCIMEM_PCI_BASE + PCIMEM_SIZE)
#define CHIP_W1_SYS_START(v)    PCIMEM_BASE
#define CHIP_W1_SYS_END(v)      (PCIMEM_BASE + PCIMEM_SIZE)

/* MEM region 2 and 3 unused */

#include <mips/mips/bus_space_alignstride_chipdep.c>
---------------------------------------------------------------
Looking at the macros in first and second file, it is 1:1 mapping for the
PCI(memory) 'BUS' and 'SYS' space. But I could not figure out why the
'BUS' address points to 0x08000000, it could be pointing to 0x00000000 as
well. ??

Third file: sys/arch/evbmips/rbtx4927/rbtx4927_bus_io.c
---------------------------------------------------------------
/*
 * Platform-specific PCI bus I/O support for the MIPS Malta.
 */

#include <sys/param.h>

#include <machine/bus.h>

#include <evbmips/rbtx4927/rbtx4927reg.h>
#include <evbmips/rbtx4927/rbtx4927var.h>

#define CHIP            rbtx4927
#define CHIP_IO         /* defined */

#define CHIP_BUS_LITTLE_ENDIAN

/* IO region */
#define CHIP_W1_BUS_START(v)    PCIIO_PCI_BASE
#define CHIP_W1_BUS_END(v)      (PCIIO_PCI_BASE + PCIIO_SIZE)
#define CHIP_W1_SYS_START(v)    PCIIO_BASE
#define CHIP_W1_SYS_END(v)      (PCIIO_BASE + PCIIO_SIZE)

#include <mips/mips/bus_space_alignstride_chipdep.c>
---------------------------------------------------------------
Looking at the macros in first and third file, it is not 1:1 mapping for
the PCI(I/O) 'BUS' and 'SYS' space. Now here it makes sense where in the
'BUS' is starting from 0x00000000 and the 'SYS' is starting from
0x16000000. 

Now the 'SYS' address space should be provided so that their won't be
overlapping with other busses, where as the 'BUS' address space of
different "protocols" are independent of each other. ??

Now as per my knowledge PCI protocol supports 40-bit address space. Now
does it include both I/O and Memory windows, OR does each have a 40-bit
address space.

Thank you for the valuable information provided.

 - Anand

-- 
http://www.fastmail.fm - One of many happy users:
  http://www.fastmail.fm/docs/quotes.html