On Mon, Feb 02, 2004 at 02:07:13PM +0530, Anand Lalgondar wrote:

> What is the significance of the following structure:
> 
> struct mips_bus_space_translation {
[...]
> I have gone through a file 'sys/arch/evbmips/rbtx4927/xxx.c' that
> contains the following code:
[...]
> #define CHIP_W1_BUS_START(v)    0x00000000UL
> #define CHIP_W1_BUS_END(v)      0xffffffffUL
> #define CHIP_W1_SYS_START(v)    0
> #define CHIP_W1_SYS_END(v)      CHIP_W1_BUS_END(v)
[...]
> How is CHIP_W1_BUS different from CHIP_W1_SYS? Both are pointing to same
> address! Is it something like physical and virtual address if so which
> one contains physical and which virtual, OR is it something else.
It is somthing else. If you have a bus bridge it may map the address
space of the bus into the addres space of the CPU with an offset. 
So you have to do a translation of bus addresses from and to CPU
addresses. CHIP_W1_BUS specifies the address range as seen on the
expansion bus and CHIP_W1_SYS specifies the same address range as 
seen from the CPU.

E.g. on a PPC PReP machine the PCI/ISA I/O address space from 0x00000000 
to 0x3fffffff is maped to the CPU address space 0x80000000 to 0xbfffffff
by the bus bridge hardware.
I.e. if you want to access the PCI/ISA I/O address 0x3f8, the CPU must
access the physical addess 0x800003f8. The correspondig #defines would be:
/* IO region 1 */
#define CHIP_W1_BUS_START(v) (0)
#define CHIP_W1_BUS_END(v)   (0x3fffffffUL)
#define CHIP_W1_SYS_START(v) (0x80000000UL)
#define CHIP_W1_SYS_END(v)   (0x80000000UL + 0x3fffffffUL)

In your example above you have a simple 1:1 mapping without offset from 
CPU addresses to bus addresses. Maybe because the hardware on this board 
has no bus bridge and all I/O is directly attached to the CPU bus.
-- 



tschüß,
         Jochen

Homepage: http://www.unixag-kl.fh-kl.de/~jkunz/