> > Hm, that might work.  The flowchart in the spec seems to indicate that
> > DRQ should be asserted before BSY is cleared, but is that guaranteed?
> 
> I think so, all the specs I've seen indicates that BSY has to be cleared
> last. Without this we could probably find senarios where a polled command
> would not work as expected.

The only problem I remember is there may be a short delay after the command
is written before BSY or DRQ is set (or DONE cleared).
For a polled command without a data transfer it is difficult to tell
whether the command has completed or nothing has happened.

(OTOH I've only coded PIO mode ATA and ATAIPI transfers for master-only
interfaces...)

	David

-- 
David Laight: david@l8s.co.uk