> Hm, that might work.  The flowchart in the spec seems to indicate that
> DRQ should be asserted before BSY is cleared, but is that guaranteed?

ATA-2 and ATA-3 say:

"The device shall not change the state of the DRQ bit unless the BSY
bit is equal to one.  [...]  When the BSY bit equals zero, the device
may only change [list that does not include DRQ]."

ATA-4 and ATA-5 say:"

"When BSY is cleared to zero, the host has control of the Command
Block registers, the device shall: [...]  1) not set DRQ to one;
[...]"

So I guess this is safe.