On Tue, 9 Sep 2003 14:03:59 +0100
David Laight <david@l8s.co.uk> wrote:

> > So I went and got ad1980 specifications.  As I understand (which may be
> > wrong...), the card needs a delay of 50ns (maximun) after a reset to be up
> > again.  So I added that delay just after the reset register is written, and
> > all problem have gone away.
> 
> > No more "code invalid" nor "codec busy".
> 
> > +	delay(50);
> 
> A 50 microsecod delay seems a little extravagent if the device only
> claims to need 50ns.

> Have you tried to find out how short a delay is needed?

I overlooked delay() units.  Well, have tried with smaller delay values but
it keeps failing.  Here are all reset related timings present in the datasheet,
in case I got them wrong:

RESET Active Low Pulsewidth - Max empty
RESER Inactive to BIT_CLK Startup Delay - Max 400,000 ns
Setup to RESET Inactive (SYNC, SDATA_OUT) - Min 15 ns, Max empty
Rising Edge of RESET to Hi-Z Delay - 25 ns
RESET Rise Time - 50 ns

> It might only be necessary to do a read from the reset register address.
> (this is necessary in order to flush the write through all the PCI
> bridges).

I have tried this in two places: just after it's written, and just before the
ID1 register is read.  The result in both cases is that ID1 is read properly,
but the "invalid codec" message still appears (this one shown by auvia.c).
(maybe the problem needs a fix in ac97, reading reset, and another one in auvia,
see below)

auvia has a TIMEOUT=50 constant that specifies how many loop iterations should
be done waiting for a read.  I guess this computer is so fast (XP2600+) that the
50 value is not enough (it's not a delay()).

> 50ns delay is only just over a single clock on a 33M PCI bus. So it is
> probably possible to time this by doing a PCI access to an appropriate
> address rather than attempting a software delay loop.

No idea... don't know how pci works :p

Thanks!

-- 
Julio M. Merino Vidal <jmmv@menta.net>
The NetBSD Project - http://www.NetBSD.org/