On Tue, Aug 19, 2003 at 09:51:30AM +0200, Daniel Brewer wrote:

> We measured the delay between rising edge of the interrupt from the add-on
> card to when the registers on the USART are being accessed with a logic
> analyser. The logic analyser was set to trigger on a long delay between the
> interrupt and the register access.

Obviously there are two possibilities:

either there is a large critical section which masks interrupts for an 
extended period of time

or

your interrupt is being preempted by something else.


A good way to detect the former problem is to add some code to the head
of your interrupt handler that traverses up the stack to the trapframe
and get the trap PC from it.  It should point to the instruction right
after the splx() lowered the interrupt priority.  

OTOH if the port you are running on simulates interrupt levels in software, 
you can instrument the interrupt dispatch code to track the state of
your interrupt and trap into the debugger if it detects your interrupt
is delayed too long.

Eduardo