Subject: Re: IST_LEVEL in arch/mips
To: None <email@example.com>
From: David Laight <firstname.lastname@example.org>
Date: 03/13/2003 08:09:24
> > Jason's suggestion was just to do:
> > #define IST_NONE 0 /* none (dummy) */
> > #define IST_PULSE 1 /* pulsed */
> > #define IST_EDGE 2 /* edge-triggered */
> > #define IST_LEVEL 3 /* level-triggered */
> > #define IST_LEVEL_LOW 4 /* level triggered, active low */
> > #define IST_LEVEL_HIGH 5 /* level triggered, active high */
> > and then just deal with it in the intr code.
> Well, that's nice, but there's no reason that edge-triggered or pulsed
> interrupts should _have_ to be high or low, either.
> (i've know gpios which can be edge or level, high or lo. 8-)
Don't forget the ones that can be be triggered on either or both edges.
David Laight: email@example.com