At 08:39 AM 2/13/2003, Jason R Thorpe wrote:

>  > c) Data in the bus_dmamap_sync footprint should not be accessed by the
>  > processor
>  >    if a BUS_DMASYNC_PREREAD is in effect for the bus_dmamap_sync 
> footprint.
>  >    ( Example: XSCALE architecture?)
>  >
>  >    Problems:
>  >     Reading data that falls in the bus_dmamap_sync footprint might 
> cause a
>  > cacheline to be loaded.
>  >     This cacheline might persist in the cache and present outdated memory
>  > state to the CPU
>  >     even after a BUS_DMASYNC_POSTREAD sync operation.
>  >     The outdated state in the cacheline can be flushed by a
>  > BUS_DMASYNC_PREREAD sync.
>  >     ( This could be fixed by  flushing cache lines on 
> BUS_DMASYNC_POSTREAD)
>
>No, I don't think this is a problem.  If you determine that the device is
>going to update the memory location again, then you issue another PREREAD,
>which will do the necessary non-writeback-invalidate.  This is what current
>drivers do.
>
>Basically, the CPU should not even try to access DMA memory (read *or* write)
>while the device "owns" it (i.e. between PRE and POST ops).

Not always possible.  Think mbufs with >1 reference counts.


-- 
Matt Thomas               Internet:   matt@3am-software.com
3am Software Foundry      WWW URL:    http://www.3am-software.com/bio/matt/
Cupertino, CA             Disclaimer: I avow all knowledge of this message