bus_dmamap_sync not enough for some devices ?

Some PCI devices use DMA to send command completion and status information to 
main memory.
(Example Intel Pro 100 - sys/dev/ic/i82257.c )

Communication between driver and device borrows tactics from SMP environments.

However, bus_dmamap_sync is not suited for this kind of communication, since 
both device and
CPU(s) need to have access to the buffer at the same time. 

What I think is missing to implement this correctly are machine-independent 
functions to access
main memory in a strongly ordered way. 
(Just declaring a structure member as volatile is not enough - in SMP the 
spinlocks
provide mutual exclusion AND strong memory ordering through memory barriers.)

I can attest to the need for ordered memory access.
A few years ago, I personally tracked down out of order CPU reads of ordered 
82257 DMA writes
on a proprietary 82257 Ethernet driver, running on a Pentium III machine.
(Just a few cases per day on stress tests - CPU reads just a few opcodes 
apart.)

Is there a clean machine-independent way to handle these devices on netbsd 
that I missed ?


Stephan


---------------------
Stephan Uphoff 
ups@stups.com
9275 Martin Road
Roswell, GA 30076
770-518-4058