Subject: Re: PXA250 Xscale and page tables
To: None <firstname.lastname@example.org>
From: David Laight <email@example.com>
Date: 02/02/2003 08:31:26
> Ok, Sorry I'm slow, are you saying that the I-Cache deals with virtual
> addresses only? So if 2 VA's mapped to the same PA, you could write to the
> first and it would sit in the cache for that address but VA 2 would not see
> it? Doesn't the caches implement some type of snoop-invalidate protocol?
> (Again sorry for foolish questions, I don't know ARM all that well).
Yes, you've got it in one.... (Except that it can't matter for the
I-cache since it is impossible to write to it.)
What is more you can invalidate the page table entry and, if you
don't flush the cache, the cpu will still read the data from the cache.
The only thing I didn't work out was whether the access bits
are stored in the cache tag...
David Laight: firstname.lastname@example.org