Subject: Re: PXA250 Xscale and page tables
To: None <firstname.lastname@example.org>
From: Colin Cook <email@example.com>
Date: 02/01/2003 10:13:55
Sorry, There *is* something grossly wrong with ALL arm32 based NetBSD code.
ptes[arm_btop(npv->pv_va)] &= ~L2_S_CACHE_MASK in pmap.c
It is removing the C bit from application CODE space. We have removed this
line and our app now runs 10X faster.
What I want to know is why was this in there in the first place. Turning off
the cache is a very bad thing to do.
On Fri, 31 Jan 2003, Colin Cook wrote:
> We have built a PXA250(B2) device and have NetBSD running. We are now
> The problem is page table entries. Our main application is running very
> and after some research we have found that the second level page table
> entries for application code are marked as non-cached, C=0 B=0. So our
> applications are running entirely out of SDRAM directly.
I think you'll find that application text/data *is* mapped cacheable,
unless there is something gossly wrong with how the pmap is initialised on
Check how the pmap module uses "pte_l2_s_cache_mode". For Xscale, this is
initialised in pmap_pte_init_xscale().
> 1) Where are the page tables setup for user application code space (in the
> source). High and low level functions would be helpful so I could see how
> was down from the point a app context is created all the way down to the
> bits being set.
Start with pmap_create(), then look at pmap_enter(). The former is called
a process creation time. The latter is called indirectly (usually) as a
result of the application taking a page-fault.
> Also is there a reference manual, book, or other material I could read to
> help me understand the pmap code (arm/arm32)
Well, the Arm ARM is the canonical reference manual for the cpu/mmu. I
would also recommend reading NetBSD's pmap(9) manual page.
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