Subject: PXA250 Xscale and page tables
To: None <firstname.lastname@example.org>
From: Colin Cook <email@example.com>
Date: 01/31/2003 08:30:47
To NetBSD Kernel Developers:
We have built a PXA250(B2) device and have NetBSD running. We are now using
The problem is page table entries. Our main application is running very slow
and after some research we have found that the second level page table
entries for application code are marked as non-cached, C=0 B=0. So our
applications are running entirely out of SDRAM directly.
I am going though pmap.c now, but this is quite complicated and I am
concerned that I might break something if I just go change stuff without
fully understanding it.
I have 2 questions for now.
1) Where are the page tables setup for user application code space (in the
source). High and low level functions would be helpful so I could see how it
was down from the point a app context is created all the way down to the pte
bits being set.
2) Why was caching turned off (or not turned on) in the first place.
Also is there a reference manual, book, or other material I could read to
help me understand the pmap code (arm/arm32)
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