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On Tue Jan 14 2003 at 13:41:11 +0900, enami tsugutomo wrote:
> Ilpo Ruotsalainen <lonewolf@iki.fi> writes:
> 
> > Could someone check that this is ok before I commit, please.
> 
> Mixing different coding style makes source code incredibly hard to read.

Sorry about that. Here's take two, with hopefully proper coding style.

-- 
Ilpo Ruotsalainen - <lonewolf@iki.fi> - http://www.iki.fi/lonewolf/

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Index: sys/dev/ic/wdc.c
===================================================================
RCS file: /cvsroot/src/sys/dev/ic/wdc.c,v
retrieving revision 1.120
diff --unified -r1.120 wdc.c
--- sys/dev/ic/wdc.c	2003/01/01 00:10:19	1.120
+++ sys/dev/ic/wdc.c	2003/01/14 12:16:48
@@ -228,29 +228,33 @@
 
 	if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_SELECT))
 		chp->wdc->select(chp,0);
-	/* assert SRST, wait for reset to complete */
-	bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh,
-	    WDSD_IBM);
-	delay(10);
-	bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
-	    WDCTL_RST | WDCTL_IDS); 
-	DELAY(1000);
-	bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
-	    WDCTL_IDS);
-	delay(1000);
-	(void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error);
-	bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT);
-	delay(10);
-
-	ret_value = __wdcwait_reset(chp, ret_value);
-	WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n",
-	    chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel,
-	    ret_value), DEBUG_PROBE);
-
-	/* if reset failed, there's nothing here */
-	if (ret_value == 0)
-		return 0;
 
+	if (chp->wdc && (chp->wdc->cap & WDC_CAPABILITY_NO_AUX) == 0) {
+		/* assert SRST, wait for reset to complete */
+		bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh,
+		    WDSD_IBM);
+		delay(10);
+		bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
+		    WDCTL_RST | WDCTL_IDS); 
+		DELAY(1000);
+		bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
+		    WDCTL_IDS);
+		delay(1000);
+		(void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error);
+		bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr,
+		    WDCTL_4BIT);
+		delay(10);
+	
+		ret_value = __wdcwait_reset(chp, ret_value);
+		WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n",
+		    chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe",
+		    chp->channel, ret_value), DEBUG_PROBE);
+	
+		/* if reset failed, there's nothing here */
+		if (ret_value == 0)
+			return 0;
+	}
+
 	/*
 	 * Test presence of drives. First test register signatures looking for
 	 * ATAPI devices. If it's not an ATAPI and reset said there may be
@@ -759,6 +763,12 @@
 	int verb;
 {
 	int drv_mask1, drv_mask2;
+
+	if (chp->wdc->cap & WDC_CAPABILITY_NO_AUX) {
+		printf("%s: unable to reset (no aux registers)\n",
+		    chp->wdc->sc_dev.dv_xname);
+		return 1;
+	}
 
 	if (chp->wdc->cap & WDC_CAPABILITY_SELECT)
 		chp->wdc->select(chp,0);
Index: sys/dev/ic/wdcvar.h
===================================================================
RCS file: /cvsroot/src/sys/dev/ic/wdcvar.h,v
retrieving revision 1.34
diff --unified -r1.34 wdcvar.h
--- sys/dev/ic/wdcvar.h	2002/01/13 17:24:29	1.34
+++ sys/dev/ic/wdcvar.h	2003/01/14 12:16:50
@@ -103,6 +103,7 @@
 #define WDC_CAPABILITY_SINGLE_DRIVE 0x0800 /* Don't probe second drive */
 #define WDC_CAPABILITY_NOIRQ  0x1000	/* Controller never interrupts */
 #define WDC_CAPABILITY_SELECT  0x2000	/* Controller selects target */
+#define WDC_CAPABILITY_NO_AUX 0x4000	/* Controller doesn't have aux ports */
 	u_int8_t      PIO_cap; /* highest PIO mode supported */
 	u_int8_t      DMA_cap; /* highest DMA mode supported */
 	u_int8_t      UDMA_cap; /* highest UDMA mode supported */

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