On Tue, Dec 10, 2002 at 12:37:15AM +0100, David Ferlier wrote:

> I think these routines shouldn't exist, but there should be tests of the arch
> with ifdefs, and inside the tests definitions of the devices paths with their
> associated ports adresses.

I don't understand what "associated ports adresses" means in this context.

Let me give you some examples:

zs0 at obio0 slot 0 offset 0x100000 level 12 softpri 6
zstty0 at zs0 channel 0 (console i/o)
zstty1 at zs0 channel 1
zs1 at obio0 slot 0 offset 0x0 level 12 softpri 6
kbd0 at zs1 channel 0: baud rate 1200
ms0 at zs1 channel 1: baud rate 1200

This are two Zilog serial chips on a sparc, each with two serial ports.
Zstty0 is the serial console on that machine (not available for applications)
and zstty1 is connected to my UPS. They are called /dev/ttya and /dev/ttyb
for historic reasons.

The two ports on the second chip (zs1) are used to connect a keyboard and
a mouse - so are not available to applications.

Same machine, a bit further down in dmesg:

bpp0 at sbus0 slot 4 offset 0xc800000 level 2 (ipl 3): dma rev 2

This is a parallel port (/dev/bpp).

Ok, another machine (sparc64):

sab0 at ebus0 addr 400000-40007f ipl 43: rev 3.2
sabtty0 at sab0 port 0: console i/o
sabtty1 at sab0 port 1
com0 at ebus0 addr 3083f8-3083ff ipl 41: ns16550a, working fifo
kbd0 at com0
com1 at ebus0 addr 3062f8-3062ff ipl 42: ns16550a, working fifo
ms0 at com1
lpt0 at ebus0 addr 3043bc-3043cb, 300398-300399, 700000-70000f ipl 34

Same scenario here, a SAB82532 Dual UART is used for serial console and
one free port, but this is called /dev/ttyh1.

Then there are some real PC-like com ports, but hey, they are used to 
connect keyboard and mouse! Last you find a standard PC "legacy" parallel
port, but can you tell it's associated port address? (hint: sparc64 has no
"inb" or "outb" instruction, but uses memory access with a specific "address
space identifier". The "addr" listed above is relative to the "ebus0" it
is connected to, you need to traverse the whole device tree to the root to
understand the final memory address this lpt0 gets mapped to)

I think you see why the concept you are talking about does only make
sense on ISA based PCs. Even in modern multiple PCI/no ISA PCs its
starting to get meaningless. That's why it's not on PCI but in the 
south/northbridge (I always mix those) on PCs nowadays.


Martin