I've found many GPIO chips (and issues) on Hpc* ports.

For example Vr CPU have embedded GPIO ports and PCI bus controller
in it and interrupt lines of chips on the PCI bus are generally connected to
the
GPIO ports. Some chips on the PCI bus have GPIO ports too.

Manufacturer can connect interrupt lines and power control lines to any
ports and interrupt lines might be inverted with outer circuit. It's
possible that
a interrupt line of  a chip on a PCI bus is connected to a GPIO port of
other
chip on the bus. Some keys on keyboard might be connected to some GPIO
ports. You can find two or more chips of same type which have GPIO ports
on a PCI bus...

Sys/arch/hpcmips/conf/GENERIC describes such port mappings. Following
lines are describtion for Victor Interlink MP-C303(Vr4122 CPU, handheld
PC).

    vr4122ip*       at mainbus0 platform GENERIC_MIPS_VR_4122
    vrgiu*  at vr4122ip? addr 0x0f000140 size 0x20 unit VRGIU
    vrpciu* at vr4122ip? addr 0x0f000c00 size 0x200 unit VRPCIU
    hpcioman7 at vrgiu? platform VICTOR_INTERLINK_MPC303
    hpcin*  at hpcioman7 evtype PCIINTR id PCIINTR_00_19_00 port 1 level 0
hold 1 connect 1

Vrgiu is CPU embedded GPIO controller and vrpciu is CPU embedded
PCI bus controller. The  interrupt line of  the chip on PCI bus 00 device 19
function 00 is connected to the port #1 of the CPU embedded GPIO
controller. Hpcin, hpcout and hpcioman are Hpc* generic GPIO drivers
and sys/arch/hpc/hpc/config_hook.c takes care of the mappings.

Takemura

----- Original Message -----
From: "Jason R Thorpe" <thorpej@wasabisystems.com>
To: <tech-kern@netbsd.org>
Sent: Tuesday, August 13, 2002 1:10 PM
Subject: RFC: General purpose "general purpose i/o pin" framework


> Folks...
>
> Soon I'm going to start work on a generic interface for manipulating
> GPIO pins.  I'm still trying to figure out exactly what it should have,
> but let me give you an idea of what I'm thinking about so far:
>
> * When a device (e.g. a generic GPIO facility in an
>   I/O processor) wishes to publish its GPIO pins to
>   the world, it requests one or more chunks of GPIO
>   "pin number" space from the GPIO framework.  A mapping
>   is then established, e.g. "gpio pin 3 -> i80321 gpio pin 3"
>   or "gpio pin 5 -> sc520 gpio pin 9".
snipped
> --
>         -- Jason R. Thorpe <thorpej@wasabisystems.com>