Subject: forcing a device to a specific irq
To: None <tech-kern@netbsd.org>
From: Joe Reed <jnr@po.cwru.edu>
List: tech-kern
Date: 08/02/2002 20:50:58
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hi all,
i'm still working on modifying the gsip driver to work with netgear's ga-621
card. i recently learned that on a wondoze system, these cards will not
operate on anything EXCEPT irq 9. looking at my dmesg, gsip0 initializes in
irq5. i'd like to force it to use irq 9 and see what happens.
what is the best way to go about doing this?
i'm running yesterday's -current(i386). i've attached a diff of
src/sys/dev/pci/if_sip.c which i have modified with some printf()'s and
also i've attached a dmesg from the resulting kernel.
--joe
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Index: if_sip.c
===================================================================
RCS file: /cvsroot/syssrc/sys/dev/pci/if_sip.c,v
retrieving revision 1.61
diff -u -r1.61 if_sip.c
--- if_sip.c 2002/07/11 18:07:56 1.61
+++ if_sip.c 2002/08/02 03:02:43
@@ -76,8 +76,6 @@
*
* TODO:
*
- * - Support the 10-bit interface on the DP83820 (for fiber).
- *
* - Reduce the Rx interrupt load.
*/
@@ -922,29 +920,37 @@
sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg;
ifmedia_init(&sc->sc_mii.mii_media, 0, SIP_DECL(mediachange),
SIP_DECL(mediastatus));
+
+/*
+ * XXX i think the ga-621 error is here
+ */
+
#ifdef DP83820
- if (sc->sc_cfg & CFG_TBI_EN) {
- /* Using ten-bit interface. */
- printf("%s: TBI -- FIXME\n", sc->sc_dev.dv_xname);
- } else {
- mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
- MII_OFFSET_ANY, 0);
- if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
- ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE,
- 0, NULL);
- ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
- } else
- ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
- }
-#else
+ printf ("%s: DEBUG: %x in config register\n",sc->sc_dev.dv_xname,reg);
+ printf ("%s: DEBUG: %x in MII_BMCR\n",sc->sc_dev.dv_xname,
+ SIP_DECL(dp83820_mii_readreg)(&(sc->sc_dev),0,MII_BMCR));
+ printf ("%s: DEBUG: %x in MII_BMSR\n",sc->sc_dev.dv_xname,
+ SIP_DECL(dp83820_mii_readreg)(&(sc->sc_dev),0,MII_BMSR));
+ printf ("%s: DEBUG: %x in MII_ANAR\n",sc->sc_dev.dv_xname,
+ SIP_DECL(dp83820_mii_readreg)(&(sc->sc_dev),0,MII_ANAR));
+ printf ("%s: DEBUG: %x in MII_ANLPAR\n",sc->sc_dev.dv_xname,
+ SIP_DECL(dp83820_mii_readreg)(&(sc->sc_dev),0,MII_ANLPAR));
+ printf ("%s: DEBUG: %x in MII_ANER\n",sc->sc_dev.dv_xname,
+ SIP_DECL(dp83820_mii_readreg)(&(sc->sc_dev),0,MII_ANER));
+ printf ("%s: DEBUG: %x in MII_EXTSR\n",sc->sc_dev.dv_xname,
+ SIP_DECL(dp83820_mii_readreg)(&(sc->sc_dev),0,MII_EXTSR));
+#endif
+
+/*end XXX*/
mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
MII_OFFSET_ANY, 0);
+
if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
- } else
+ } else {
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
-#endif /* DP83820 */
+ }
ifp = &sc->sc_ethercom.ec_if;
strcpy(ifp->if_xname, sc->sc_dev.dv_xname);
@@ -2842,7 +2848,72 @@
int
SIP_DECL(dp83820_mii_readreg)(struct device *self, int phy, int reg)
{
+ struct sip_softc *sc = (void *) self;
+ if (sc->sc_cfg & CFG_TBI_EN) {
+/* XXX */
+ bus_addr_t tbireg;
+ int rv;
+
+ printf("%s: MII_READREG_DEBUG:",sc->sc_dev.dv_xname);
+
+ if (phy != 0) {
+ printf(" phy == %x (!=0), returning with error\n",phy);
+ return (0);
+ }
+
+/*XXX*/ printf (" phy good (%x). Reading ",phy);
+
+ switch (reg) {
+ case MII_BMCR: tbireg = SIP_TBICR;
+ printf("MII_BMCR "); break;
+ case MII_BMSR: tbireg = SIP_TBISR;
+ printf("MII_BMSR "); break;
+ case MII_ANAR: tbireg = SIP_TANAR;
+ printf("MII_ANAR "); break;
+ case MII_ANLPAR: tbireg = SIP_TANLPAR;
+ printf("MII_ANLPAR "); break;
+ case MII_ANER: tbireg = SIP_TANER;
+ printf("MII_ANER "); break;
+ case MII_EXTSR: tbireg = SIP_TESR;
+ printf("MII_EXTSR "); break;
+ default:
+ printf ("nothing. error_invalid_reg: 0x%x\n",reg);
+ return (0);
+ }
+
+ printf(" (%x) register\n",(int)tbireg);
+
+ rv = bus_space_read_4(sc->sc_st, sc->sc_sh, tbireg) & 0xffffffff;
+
+ if (tbireg == SIP_TBISR)
+ rv |= TBISR_MR_LINK_STATUS | 0x0100;
+
+ printf("%s: MII_READREG_DEBUG: Read %x from MII register\n",sc->sc_dev.dv_xname,rv);
+
+ if (tbireg == SIP_TBISR) {
+ /* LINK and ACOMP are switched! */
+ int val = rv;
+
+ printf("%s: MII_READREG_DEBUG: swapping Link and ACOMP",sc->sc_dev.dv_xname);
+
+ rv = 0;
+ if (val & TBISR_MR_LINK_STATUS) {
+ printf(" %x & BMSR_LINK",rv);
+ rv |= BMSR_LINK;
+ }
+
+ if (val & TBISR_MR_AN_COMPLETE) {
+ printf(" %x & BSMR_ACOMP",rv);
+ rv |= BMSR_ACOMP;
+ }
+ printf("\n");
+ }
+
+ printf("%s: MII_READREG_DEBUG: returning: %x\n",sc->sc_dev.dv_xname,rv);
+ return (rv);
+ }
+
return (mii_bitbang_readreg(self, &SIP_DECL(dp83820_mii_bitbang_ops),
phy, reg));
}
@@ -2855,6 +2926,35 @@
void
SIP_DECL(dp83820_mii_writereg)(struct device *self, int phy, int reg, int val)
{
+ struct sip_softc *sc = (void *) self;
+
+ if (sc->sc_cfg & CFG_TBI_EN) {
+ bus_addr_t tbireg;
+
+ /* XXX */
+ printf("%s: MII_WRITEREG_DEBUG: ",sc->sc_dev.dv_xname);
+
+ if (phy != 0) {
+ printf("phy != 0, returning 0\n");
+ return;
+ }
+
+ printf ("writing: %x to ",val);
+
+ switch (reg) {
+ case MII_BMCR: tbireg = SIP_TBICR; printf("MII_BMCR"); break;
+ case MII_ANAR: tbireg = SIP_TANAR; printf("MII_ANAR"); break;
+ case MII_ANLPAR: tbireg = SIP_TANLPAR; printf("MII_ANLPAR"); break;
+ default:
+ printf("invalid_register\n");
+ return;
+ }
+
+ printf ("register\n");
+
+ bus_space_write_4(sc->sc_st, sc->sc_sh, tbireg, val);
+ return;
+ }
mii_bitbang_writereg(self, &SIP_DECL(dp83820_mii_bitbang_ops),
phy, reg, val);
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ures 183f9ff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,SEP,MTRR>
cpu0: features 183f9ff<PGE,MCA,CMOV,FGPAT,PSE36,MMX>
cpu0: features 183f9ff<FXSR>
total memory = 255 MB
avail memory = 230 MB
using 3296 buffers containing 13184 KB of memory
BIOS32 rev. 0 found at 0xfdb10
mainbus0 (root)
pci0 at mainbus0 bus 0: configuration mode 1
pci0: i/o space, memory space enabled, rd/line, rd/mult, wr/inv ok
pchb0 at pci0 dev 0 function 0
pchb0: VIA Technologies VT8363 KT133 System Controller (rev. 0x81)
agp0 at pchb0: aperture at 0xe0000000, size 0x10000000
ppb0 at pci0 dev 1 function 0: VIA Technologies VT8363 KT133 PCI to AGP Bridge (rev. 0x00)
pci1 at ppb0 bus 1
pci1: i/o space, memory space enabled
vga1 at pci1 dev 0 function 0: Nvidia Corporation RIVA TNT2 (rev. 0x11)
wsdisplay0 at vga1 kbdmux 1: console (80x25, vt100 emulation)
wsmux1: connecting to wsdisplay0
pcib0 at pci0 dev 7 function 0
pcib0: VIA Technologies VT82C686A (Apollo KX133) PCI-ISA Bridge (rev. 0x40)
pciide0 at pci0 dev 7 function 1: VIA Technologies VT82C686A (Apollo KX133) ATA100 controller
pciide0: bus-master DMA support present
pciide0: primary channel configured to compatibility mode
atapibus0 at pciide0 channel 0: 2 targets
cd0 at atapibus0 drive 1: <EPO CD-ROM CR-840S, , Ver3.07> type 5 cdrom removable
cd0: 32-bit data port
cd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 2 (Ultra/33)
wd0 at pciide0 channel 0 drive 0: <WDC WD205BA>
wd0: drive supports 16-sector PIO transfers, LBA addressing
wd0: 19574 MB, 16383 cyl, 16 head, 63 sec, 512 bytes/sect x 40088160 sectors
wd0: 32-bit data port
wd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 4 (Ultra/66)
pciide0: primary channel interrupting at irq 14
wd0(pciide0:0:0): using PIO mode 4, Ultra-DMA mode 4 (Ultra/66) (using DMA data transfers)
cd0(pciide0:0:1): using PIO mode 4, Ultra-DMA mode 2 (Ultra/33) (using DMA data transfers)
pciide0: secondary channel configured to compatibility mode
atapibus1 at pciide0 channel 1: 2 targets
cd1 at atapibus1 drive 0: <Hewlett-Packard CD-Writer Plus 9100, YM4958RBT8, 1.0a> type 5 cdrom removable
cd1: 32-bit data port
cd1: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 2 (Ultra/33)
pciide0: secondary channel interrupting at irq 15
cd1(pciide0:1:0): using PIO mode 4, Ultra-DMA mode 2 (Ultra/33) (using DMA data transfers)
uhci0 at pci0 dev 7 function 2: VIA Technologies VT83C572 USB Controller (rev. 0x1a)
uhci0: interrupting at irq 5
usb0 at uhci0: USB revision 1.0
uhub0 at usb0
uhub0: VIA Technologie UHCI root hub, class 9/0, rev 1.00/1.00, addr 1
uhub0: 2 ports with 2 removable, self powered
uhci1 at pci0 dev 7 function 3: VIA Technologies VT83C572 USB Controller (rev. 0x1a)
uhci1: interrupting at irq 5
usb1 at uhci1: USB revision 1.0
uhub1 at usb1
uhub1: VIA Technologie UHCI root hub, class 9/0, rev 1.00/1.00, addr 1
uhub1: 2 ports with 2 removable, self powered
VIA Technologies VT82C686A SMBus Controller (miscellaneous bridge, revision 0x40) at pci0 dev 7 function 4 not configured
ex0 at pci0 dev 9 function 0: 3Com 3c905B-TX 10/100 Ethernet (rev. 0x30)
ex0: interrupting at irq 3
ex0: MAC address 00:50:04:9b:b4:06
exphy0 at ex0 phy 24: 3Com internal media interface
exphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
eap0 at pci0 dev 14 function 0: Ensoniq CT5880 CT5880C (rev. 0x02)
eap0: interrupting at irq 10
eap0: SigmaTel STAC9708 codec; 18 bit DAC, 18 bit ADC, SigmaTel 3D
audio0 at eap0: full duplex, mmap, independent
midi0 at eap0: AudioPCI MIDI UART
gsip0 at pci0 dev 15 function 0: NatSemi DP83820 Gigabit Ethernet, rev 00
gsip0: interrupting at irq 5
gsip0: Ethernet address 00:40:f4:59:4c:44
gsip0: using ten-bit interface
gsip0: DEBUG: 81401000 in config register
gsip0: MII_READREG_DEBUG: phy good (0). Reading MII_BMCR (e0) register
gsip0: MII_READREG_DEBUG: Read 0 from MII register
gsip0: MII_READREG_DEBUG: returning: 0
gsip0: DEBUG: 0 in MII_BMCR
gsip0: MII_READREG_DEBUG: phy good (0). Reading MII_BMSR (e4) register
gsip0: MII_READREG_DEBUG: Read 124 from MII register
gsip0: MII_READREG_DEBUG: swapping Link and ACOMP 0 & BMSR_LINK 4 & BSMR_ACOMP
gsip0: MII_READREG_DEBUG: returning: 24
gsip0: DEBUG: 24 in MII_BMSR
gsip0: MII_READREG_DEBUG: phy good (0). Reading MII_ANAR (e8) register
gsip0: MII_READREG_DEBUG: Read 0 from MII register
gsip0: MII_READREG_DEBUG: returning: 0
gsip0: DEBUG: 0 in MII_ANAR
gsip0: MII_READREG_DEBUG: phy good (0). Reading MII_ANLPAR (ec) register
gsip0: MII_READREG_DEBUG: Read 0 from MII register
gsip0: MII_READREG_DEBUG: returning: 0
gsip0: DEBUG: 0 in MII_ANLPAR
gsip0: MII_READREG_DEBUG: phy good (0). Reading MII_ANER (f0) register
gsip0: MII_READREG_DEBUG: Read 4 from MII register
gsip0: MII_READREG_DEBUG: returning: 4
gsip0: DEBUG: 4 in MII_ANER
gsip0: MII_READREG_DEBUG: phy good (0). Reading MII_EXTSR (f4) register
gsip0: MII_READREG_DEBUG: Read 0 from MII register
gsip0: MII_READREG_DEBUG: returning: 0
gsip0: DEBUG: 0 in MII_EXTSR
gsip0: MII_READREG_DEBUG: phy good (0). Reading MII_BMSR (e4) register
gsip0: MII_READREG_DEBUG: Read 124 from MII register
gsip0: MII_READREG_DEBUG: swapping Link and ACOMP 0 & BMSR_LINK 4 & BSMR_ACOMP
gsip0: MII_READREG_DEBUG: returning: 24
gsip0: MII_READREG_DEBUG: phy == 1 (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == 2 (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == 3 (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == 4 (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == 5 (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == 6 (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == 7 (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == 8 (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == 9 (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == a (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == b (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == c (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == d (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == e (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == f (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == 10 (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == 11 (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == 12 (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == 13 (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == 14 (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == 15 (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == 16 (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == 17 (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == 18 (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == 19 (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == 1a (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == 1b (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == 1c (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == 1d (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == 1e (!=0), returning with error
gsip0: MII_READREG_DEBUG: phy == 1f (!=0), returning with error
isa0 at pcib0
com0 at isa0 port 0x3f8-0x3ff irq 4: ns16550a, working fifo
pckbc0 at isa0 port 0x60-0x64
pckbd0 at pckbc0 (kbd slot)
pckbc0: using irq 1 for kbd slot
wskbd0 at pckbd0: console keyboard, using wsdisplay0
pms0 at pckbc0 (aux slot)
pckbc0: using irq 12 for aux slot
wsmouse0 at pms0 mux 0
lpt0 at isa0 port 0x378-0x37b irq 7
pcppi0 at isa0 port 0x61
midi1 at pcppi0: PC speaker
sysbeep0 at pcppi0
isapnp0 at isa0 port 0x279: ISA Plug 'n Play device support
npx0 at isa0 port 0xf0-0xff: using exception 16
fdc0 at isa0 port 0x3f0-0x3f7 irq 6 drq 2
fd0 at fdc0 drive 0: 1.44MB, 80 cyl, 2 head, 18 sec
isapnp0: no ISA Plug 'n Play devices found
biomask eb65 netmask eb6d ttymask fbef
Kernelized RAIDframe activated
uhub0: port error, restarting port 1
uhub0: port error, giving up port 1
uhub1: port error, restarting port 1
uhub1: port error, giving up port 1
uhub1: port error, restarting port 2
uhub1: port error, giving up port 2
boot device: wd0
root on wd0a dumps on wd0b
root file system type: ffs
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