Subject: Trimming down pciide.o
To: None <tech-kern@netbsd.org>
From: Simon Burge <simonb@wasabisystems.com>
List: tech-kern
Date: 07/31/2002 14:35:03
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While looking at trimming down a kernel I noticed that one of the
largest objects is pciide.o. Since the particular board I was looking
at only had a PIIX pciide controller, I've added some options so that we
can select only a subset of all pciide controllers we support.
As an example, adding:
options PCIIDE_RESTRICTED_SUPPORT # don't enable all pciide support
options PCIIDE_PIIX_ENABLE # enable PIIX support
to my kernel config results in pciide.o shrinking quite a lot:
text data bss dec hex filename
44752 80 0 44832 af20 pciide.o.before
13368 80 0 13448 3488 pciide.o.after
What do people think of this?
Simon.
--
Simon Burge <simonb@wasabisystems.com>
NetBSD Development, Support and Service: http://www.wasabisystems.com/
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Index: files.pci
===================================================================
RCS file: /cvsroot/syssrc/sys/dev/pci/files.pci,v
retrieving revision 1.175
diff -d -p -u -r1.175 files.pci
--- files.pci 2002/06/23 20:36:26 1.175
+++ files.pci 2002/07/31 04:30:17
@@ -12,8 +12,14 @@ defflag opt_bktr.h BKTR_430_FX_MODE BKTR
defparam opt_bktr.h BKTR_OVERRIDE_CARD BKTR_OVERRIDE_TUNER BKTR_OVERRIDE_DBX
BKTR_OVERRIDE_MSP BKTR_SYSTEM_DEFAULT
-defflag opt_pciide.h PCIIDE_CMD064x_DISABLE PCIIDE_AMD756_ENABLEDMA
- PCIIDE_CMD0646U_ENABLEUDMA
+defflag opt_pciide.h PCIIDE_CMD064x_DISABLE PCIIDE_CMD0646U_ENABLEUDMA
+ PCIIDE_AMD756_ENABLEDMA
+ PCIIDE_RESTRICTED_SUPPORT
+ PCIIDE_ACARD_ENABLE PCIIDE_ACER_ENABLE PCIIDE_AMD_ENABLE
+ PCIIDE_APOLLO_ENABLE PCIIDE_CMD_ENABLE PCIIDE_CY_ENABLE
+ PCIIDE_HPT_ENABLE PCIIDE_OPTI_ENABLE PCIIDE_PDC_ENABLE
+ PCIIDE_PIIX_ENABLE PCIIDE_SERVERWORKS_ENABLE
+ PCIIDE_SIS_ENABLE PCIIDE_WINBOND_ENABLE
device pci {[dev = -1], [function = -1]}
attach pci at pcibus
Index: pciide.c
===================================================================
RCS file: /cvsroot/syssrc/sys/dev/pci/pciide.c,v
retrieving revision 1.163
diff -d -p -u -r1.163 pciide.c
--- pciide.c 2002/07/30 21:01:57 1.163
+++ pciide.c 2002/07/31 04:30:23
@@ -79,7 +79,7 @@
__KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.163 2002/07/30 21:01:57 bouyer Exp $");
#ifndef WDCDEBUG
-#define WDCDEBUG
+// #define WDCDEBUG
#endif
#define DEBUG_DMA 0x01
@@ -123,6 +123,22 @@ int wdcdebug_pciide_mask = 0;
#include "opt_pciide.h"
+#ifndef PCIIDE_RESTRICTED_SUPPORT
+#define PCIIDE_PIIX_ENABLE
+#define PCIIDE_AMD_ENABLE
+#define PCIIDE_APOLLO_ENABLE
+#define PCIIDE_CMD_ENABLE
+#define PCIIDE_CY_ENABLE
+#define PCIIDE_SIS_ENABLE
+#define PCIIDE_ACER_ENABLE
+#define PCIIDE_PDC_ENABLE
+#define PCIIDE_OPTI_ENABLE
+#define PCIIDE_HPT_ENABLE
+#define PCIIDE_ACARD_ENABLE
+#define PCIIDE_SERVERWORKS_ENABLE
+#define PCIIDE_SL82C105_ENABLE
+#endif /* !PCIIDE_RESTRICTED_SUPPORT */
+
/* inlines for reading/writing 8-bit PCI registers */
static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t,
int));
@@ -157,19 +173,32 @@ pciide_pci_write(pc, pa, reg, val)
void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
+#ifdef PCIIDE_SERVERWORKS_ENABLE
+#ifndef PCIIDE_PIIX_ENABLE
+#define PCIIDE_PIIX_ENABLE
+#endif
+#endif
+
+#ifdef PCIIDE_PIIX_ENABLE
void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
void piix_setup_channel __P((struct channel_softc*));
void piix3_4_setup_channel __P((struct channel_softc*));
static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t));
static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*));
static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t));
+#endif /* PCIIDE_PIIX_ENABLE */
+#ifdef PCIIDE_AMD_ENABLE
void amd7x6_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
void amd7x6_setup_channel __P((struct channel_softc*));
+#endif /* PCIIDE_AMD_ENABLE */
+#ifdef PCIIDE_APOLLO_ENABLE
void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
void apollo_setup_channel __P((struct channel_softc*));
+#endif /* PCIIDE_APOLLO_ENABLE */
+#ifdef PCIIDE_CMD_ENABLE
void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
void cmd0643_9_setup_channel __P((struct channel_softc*));
@@ -181,41 +210,64 @@ void cmd680_chip_map __P((struct pciide_
void cmd680_setup_channel __P((struct channel_softc*));
void cmd680_channel_map __P((struct pci_attach_args *,
struct pciide_softc *, int));
+#endif /* PCIIDE_CMD_ENABLE */
+#ifdef PCIIDE_CY_ENABLE
void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
void cy693_setup_channel __P((struct channel_softc*));
+#endif /* PCIIDE_CY_ENABLE */
+#ifdef PCIIDE_SIS_ENABLE
void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
void sis_setup_channel __P((struct channel_softc*));
static int sis_hostbr_match __P(( struct pci_attach_args *));
+#endif /* PCIIDE_SIS_ENABLE */
+#ifdef PCIIDE_ACER_ENABLE
void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
void acer_setup_channel __P((struct channel_softc*));
int acer_pci_intr __P((void *));
+#endif /* PCIIDE_ACER_ENABLE */
+#ifdef PCIIDE_PDC_ENABLE
void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
void pdc202xx_setup_channel __P((struct channel_softc*));
void pdc20268_setup_channel __P((struct channel_softc*));
int pdc202xx_pci_intr __P((void *));
int pdc20265_pci_intr __P((void *));
+#endif /* PCIIDE_PDC_ENABLE */
+#ifdef PCIIDE_OPTI_ENABLE
void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
void opti_setup_channel __P((struct channel_softc*));
+#endif /* PCIIDE_OPTI_ENABLE */
+#ifdef PCIIDE_HPT_ENABLE
void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
void hpt_setup_channel __P((struct channel_softc*));
int hpt_pci_intr __P((void *));
+#endif /* PCIIDE_HPT_ENABLE */
+#ifdef PCIIDE_ACARD_ENABLE
void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
void acard_setup_channel __P((struct channel_softc*));
int acard_pci_intr __P((void *));
+#endif /* PCIIDE_ACARD_ENABLE */
+#ifdef PCIIDE_WINBOND_ENABLE
+void winbond_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
+#endif /* PCIIDE_WINBOND_ENABLE */
+
+#ifdef PCIIDE_SERVERWORKS_ENABLE
void serverworks_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
void serverworks_setup_channel __P((struct channel_softc*));
int serverworks_pci_intr __P((void *));
+#endif /* PCIIDE_SERVERWORKS_ENABLE */
+#ifdef PCIIDE_SL82C105_ENABLE
void sl82c105_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
void sl82c105_setup_channel __P((struct channel_softc*));
+#endif /* PCIIDE_SL82C105_ENABLE */
void pciide_channel_dma_setup __P((struct pciide_channel *));
int pciide_dma_table_setup __P((struct pciide_softc*, int, int));
@@ -245,6 +297,7 @@ const struct pciide_product_desc default
default_chip_map,
};
+#ifdef PCIIDE_PIIX_ENABLE
const struct pciide_product_desc pciide_intel_products[] = {
{ PCI_PRODUCT_INTEL_82092AA,
0,
@@ -312,7 +365,9 @@ const struct pciide_product_desc pciide_
NULL
}
};
+#endif /* PCIIDE_PIIX_ENABLE */
+#ifdef PCIIDE_AMD_ENABLE
const struct pciide_product_desc pciide_amd_products[] = {
{ PCI_PRODUCT_AMD_PBC756_IDE,
0,
@@ -340,7 +395,9 @@ const struct pciide_product_desc pciide_
NULL
}
};
+#endif /* PCIIDE_AMD_ENABLE */
+#ifdef PCIIDE_CMD_ENABLE
const struct pciide_product_desc pciide_cmd_products[] = {
{ PCI_PRODUCT_CMDTECH_640,
0,
@@ -378,7 +435,9 @@ const struct pciide_product_desc pciide_
NULL
}
};
+#endif /* PCIIDE_CMD_ENABLE */
+#ifdef PCIIDE_APOLLO_ENABLE
const struct pciide_product_desc pciide_via_products[] = {
{ PCI_PRODUCT_VIATECH_VT82C586_IDE,
0,
@@ -396,7 +455,9 @@ const struct pciide_product_desc pciide_
NULL
}
};
+#endif /* PCIIDE_APOLLO_ENABLE */
+#ifdef PCIIDE_CY_ENABLE
const struct pciide_product_desc pciide_cypress_products[] = {
{ PCI_PRODUCT_CONTAQ_82C693,
IDE_16BIT_IOSPACE,
@@ -409,7 +470,9 @@ const struct pciide_product_desc pciide_
NULL
}
};
+#endif /* PCIIDE_CY_ENABLE */
+#ifdef PCIIDE_SIS_ENABLE
const struct pciide_product_desc pciide_sis_products[] = {
{ PCI_PRODUCT_SIS_5597_IDE,
0,
@@ -422,7 +485,9 @@ const struct pciide_product_desc pciide_
NULL
}
};
+#endif /* PCIIDE_SIS_ENABLE */
+#ifdef PCIIDE_ACER_ENABLE
const struct pciide_product_desc pciide_acer_products[] = {
{ PCI_PRODUCT_ALI_M5229,
0,
@@ -435,7 +500,9 @@ const struct pciide_product_desc pciide_
NULL
}
};
+#endif /* PCIIDE_ACER_ENABLE */
+#ifdef PCIIDE_PDC_ENABLE
const struct pciide_product_desc pciide_promise_products[] = {
{ PCI_PRODUCT_PROMISE_ULTRA33,
IDE_PCI_CLASS_OVERRIDE,
@@ -478,7 +545,9 @@ const struct pciide_product_desc pciide_
NULL
}
};
+#endif /* PCIIDE_PDC_ENABLE */
+#ifdef PCIIDE_OPTI_ENABLE
const struct pciide_product_desc pciide_opti_products[] = {
{ PCI_PRODUCT_OPTI_82C621,
0,
@@ -501,7 +570,9 @@ const struct pciide_product_desc pciide_
NULL
}
};
+#endif /* PCIIDE_OPTI_ENABLE */
+#ifdef PCIIDE_HPT_ENABLE
const struct pciide_product_desc pciide_triones_products[] = {
{ PCI_PRODUCT_TRIONES_HPT366,
IDE_PCI_CLASS_OVERRIDE,
@@ -519,7 +590,9 @@ const struct pciide_product_desc pciide_
NULL
}
};
+#endif /* PCIIDE_HPT_ENABLE */
+#ifdef PCIIDE_ACARD_ENABLE
const struct pciide_product_desc pciide_acard_products[] = {
{ PCI_PRODUCT_ACARD_ATP850U,
IDE_PCI_CLASS_OVERRIDE,
@@ -542,7 +615,9 @@ const struct pciide_product_desc pciide_
NULL
}
};
+#endif /* PCIIDE_ACARD_ENABLE */
+#ifdef PCIIDE_SERVERWORKS_ENABLE
const struct pciide_product_desc pciide_serverworks_products[] = {
{ PCI_PRODUCT_SERVERWORKS_OSB4_IDE,
0,
@@ -559,7 +634,9 @@ const struct pciide_product_desc pciide_
NULL,
}
};
+#endif /* PCIIDE_SERVERWORKS_ENABLE */
+#ifdef PCIIDE_SL82C105_ENABLE
const struct pciide_product_desc pciide_symphony_products[] = {
{ PCI_PRODUCT_SYMPHONY_82C105,
0,
@@ -571,7 +648,9 @@ const struct pciide_product_desc pciide_
NULL,
}
};
+#endif
+#ifdef PCIIDE_WINBOND_ENABLE
const struct pciide_product_desc pciide_winbond_products[] = {
{ PCI_PRODUCT_WINBOND_W83C553F_1,
0,
@@ -583,6 +662,7 @@ const struct pciide_product_desc pciide_
NULL,
}
};
+#endif /* PCIIDE_WINBOND_ENABLE */
struct pciide_vendor_desc {
u_int32_t ide_vendor;
@@ -590,20 +670,48 @@ struct pciide_vendor_desc {
};
const struct pciide_vendor_desc pciide_vendors[] = {
+#ifdef PCIIDE_PIIX_ENABLE
{ PCI_VENDOR_INTEL, pciide_intel_products },
+#endif
+#ifdef PCIIDE_CMD_ENABLE
{ PCI_VENDOR_CMDTECH, pciide_cmd_products },
+#endif
+#ifdef PCIIDE_APOLLO_ENABLE
{ PCI_VENDOR_VIATECH, pciide_via_products },
+#endif
+#ifdef PCIIDE_CY_ENABLE
{ PCI_VENDOR_CONTAQ, pciide_cypress_products },
+#endif
+#ifdef PCIIDE_SIS_ENABLE
{ PCI_VENDOR_SIS, pciide_sis_products },
+#endif
+#ifdef PCIIDE_ACER_ENABLE
{ PCI_VENDOR_ALI, pciide_acer_products },
+#endif
+#ifdef PCIIDE_PDC_ENABLE
{ PCI_VENDOR_PROMISE, pciide_promise_products },
+#endif
+#ifdef PCIIDE_AMD_ENABLE
{ PCI_VENDOR_AMD, pciide_amd_products },
+#endif
+#ifdef PCIIDE_OPTI_ENABLE
{ PCI_VENDOR_OPTI, pciide_opti_products },
+#endif
+#ifdef PCIIDE_HPT_ENABLE
{ PCI_VENDOR_TRIONES, pciide_triones_products },
+#endif
+#ifdef PCIIDE_ACARD_ENABLE
{ PCI_VENDOR_ACARD, pciide_acard_products },
+#endif
+#ifdef PCIIDE_SERVERWORKS_ENABLE
{ PCI_VENDOR_SERVERWORKS, pciide_serverworks_products },
+#endif
+#ifdef PCIIDE_SL82C105_ENABLE
{ PCI_VENDOR_SYMPHONY, pciide_symphony_products },
+#endif
+#ifdef PCIIDE_WINBOND_ENABLE
{ PCI_VENDOR_WINBOND, pciide_winbond_products },
+#endif
{ 0, NULL }
};
@@ -1500,6 +1608,7 @@ next:
}
}
+#ifdef PCIIDE_PIIX_ENABLE
void
piix_chip_map(sc, pa)
struct pciide_softc *sc;
@@ -1968,7 +2077,9 @@ piix_setup_sidetim_timings(mode, dma, ch
return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) |
PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel);
}
+#endif /* PCIIDE_PIIX_ENABLE */
+#ifdef PCIIDE_AMD_ENABLE
void
amd7x6_chip_map(sc, pa)
struct pciide_softc *sc;
@@ -2138,7 +2249,9 @@ pio: /* setup PIO mode */
pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM, datatim_reg);
pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA, udmatim_reg);
}
+#endif /* PCIIDE_AMD_ENABLE */
+#ifdef PCIIDE_APOLLO_ENABLE
void
apollo_chip_map(sc, pa)
struct pciide_softc *sc;
@@ -2356,7 +2469,9 @@ pio: /* setup PIO mode */
pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg);
pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg);
}
+#endif /* PCIIDE_APOLLO_ENABLE */
+#ifdef PCIIDE_CMD_ENABLE
void
cmd_channel_map(pa, sc, channel)
struct pci_attach_args *pa;
@@ -2884,7 +2999,9 @@ cmd680_setup_channel(chp)
}
pciide_print_modes(cp);
}
+#endif /* PCIIDE_CMD_ENABLE */
+#ifdef PCIIDE_CY_ENABLE
void
cy693_chip_map(sc, pa)
struct pciide_softc *sc;
@@ -3046,7 +3163,9 @@ cy693_setup_channel(chp)
IDEDMA_CTL, idedma_ctl);
}
}
+#endif /* PCIIDE_CY_ENABLE */
+#ifdef PCIIDE_SIS_ENABLE
static int
sis_hostbr_match(pa)
struct pci_attach_args *pa;
@@ -3213,7 +3332,9 @@ pio: sis_tim |= sis_pio_act[drvp->PIO_m
}
pciide_print_modes(cp);
}
+#endif /* PCIIDE_SIS_ENABLE */
+#ifdef PCIIDE_ACER_ENABLE
void
acer_chip_map(sc, pa)
struct pciide_softc *sc;
@@ -3430,7 +3551,9 @@ acer_pci_intr(arg)
}
return rv;
}
+#endif /* PCIIDE_ACER_ENABLE */
+#ifdef PCIIDE_HPT_ENABLE
void
hpt_chip_map(sc, pa)
struct pciide_softc *sc;
@@ -3518,8 +3641,8 @@ hpt_chip_map(sc, pa)
}
for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
cp = &sc->pciide_channels[i];
+ compatchan = i;
if (sc->sc_wdcdev.nchannels > 1) {
- compatchan = i;
if((pciide_pci_read(sc->sc_pc, sc->sc_tag,
HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) {
printf("%s: %s channel ignored (disabled)\n",
@@ -3670,8 +3793,9 @@ hpt_pci_intr(arg)
}
return rv;
}
-
+#endif /* PCIIDE_HPT_ENABLE */
+#ifdef PCIIDE_PDC_ENABLE
/* Macros to test product */
#define PDC_IS_262(sc) \
((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \
@@ -4068,7 +4192,9 @@ pdc20265_pci_intr(arg)
}
return rv;
}
+#endif /* PCIIDE_PDC_ENABLE */
+#ifdef PCIIDE_OPTI_ENABLE
void
opti_chip_map(sc, pa)
struct pciide_softc *sc;
@@ -4240,7 +4366,9 @@ opti_setup_channel(chp)
pciide_print_modes(cp);
}
+#endif /* PCIIDE_OPTI_ENABLE */
+#ifdef PCIIDE_ACARD_ENABLE
#define ACARD_IS_850(sc) \
((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U)
@@ -4461,7 +4589,9 @@ acard_pci_intr(arg)
}
return rv;
}
+#endif /* PCIIDE_ACARD_ENABLE */
+#ifdef PCIIDE_SL82C105_ENABLE
static int
sl82c105_bugchk(struct pci_attach_args *pa)
{
@@ -4613,7 +4743,9 @@ sl82c105_setup_channel(chp)
pciide_print_modes(cp);
}
+#endif /* PCIIDE_SL82C105_ENABLE */
+#ifdef PCIIDE_SERVERWORKS_ENABLE
void
serverworks_chip_map(sc, pa)
struct pciide_softc *sc;
@@ -4782,3 +4914,4 @@ serverworks_pci_intr(arg)
}
return rv;
}
+#endif /* PCIIDE_SERVERWORKS_ENABLE */
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