cgd@broadcom.com asked;

> Does the PPC860 have a real TLB, and enough entries, and a translation
> architecture such that doing a "virtual page table" is practical,
> desirable?  (Doing that is fairly desirable, on MIPS.)

It's possible to implement VPT stuff on MPC860/850.  They provides special
registers to facilitate PTE tree table-walk   Masanari Tsubai once implemented
pmap module for MPC860, arbeiting largely from i386.  It could be done
smarter if it was crafted from vacuum, and the resulting would be very close
each other from MIPS, SH3, m88k and the MPC.

Regarding to the original Matt Thomas' Q;  I'm sceptical a bit to have a common
pmap across such the processors due to the implementation diversity of cache and/or
TLB machineries.  It's better to leave the processor family thrive in their own
performance enhancement tweaks having similar pmap.c's in parallel, I think.

Toru Nishimura/ALKYL Technology