> 
> A PCI bus should be able to handle a 100Mb data stream, it's less than
            ^^^^^^
> 10% of its capacity.

SHOULD is the appropriate word!
Modern PC northbridge chips (probably) have a reasonable data path
into memory, the same could not be said for some of the earlier
silicon we (keeping the company name out of things) were trying to
use for pentium-pro servers. 100M just didn't work!

However to get burst reads to work the bridge chips (probably) need to
know that the target address is memory.  The bios almost certainly
sets up the host/north bridge, but the subsidiary bridges may also
need to be told. The initiator can issue read-multiple or read-line
requests - which would be a hint.

The situation for writes is different.  Memory Write and Invalitate
(MWI) cycles can only be used if the transfer is an integral number
of cache lines.  The source device (and probably all the intervening
bridges) have to be told the cache line size.
Writes will (probably) generate bursts because of write posting.

Do you know if the receive side or transmit side is failing?

	David

(Unfortunately I've only got the PCI 2.0 spec which predates bridges)

-- 
David Laight: david@l8s.co.uk