On Mon, Jun 24, 2002 at 06:05:25PM +0100, David Laight wrote:
> > Thanks, I'll try this. But I also get the problem when using only one of the
> > interfaces of the DFE580 (using an extra etherpowerII to act as router), so
> > it seems that the problem is when there is concurent activity on either
> > the primary or secondary PCI bus.
> 
> In that case it stinks of problems with the bandwith from the PCI bus
> into main memory........

A PCI bus should be able to handle a 100Mb data stream, it's less than
10% of its capacity.
I had the same problem with the D-Link DFE570, which has 4 DEC 21143 behind
the same PCI bridge, but in normal operations I only get a RX overrun
once in a while. It may be because the 21143 has a larger receive fifo ...

I tried various settings in PCI config registers, and dumping config registers.
I also tried another motherboard (VIA based). Things are worse with the
VIA.

One interesting test it disabling the memory write and invalidate
bit in the sundance's standart PCI config register, and the DMA register.
This doens't make any difference. It really looks like memory write and
invalidate are really not used. Maybe the sundance is buggy and never
issue memory write and invalidate commands. Maybe the PCI/PCI bridge is
buggy or misconfigured and translate them in memory write.
The cache line size register is properly set on both the bridge and the
sundance chips.

The MWI bit on the pci/pci bridge is hardwired to 0. The doc says it's
because the bridge issue MWI only when operating on behalf of another master
which is issuing a MWI. I can't see this as a problem, unless the BIOS
look at this bit to to some setup on the chipset for devices which can
do MWI. Does anyone know if a PCI chipset needs a per-slot setup for MWI
PCI commands ?

--
Manuel Bouyer, LIP6, Universite Paris VI.           Manuel.Bouyer@lip6.fr
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