On Sat, Jun 22, 2002 at 08:57:01AM +0100, David Laight wrote:
> > 
> > $ Does anyone have an idea on what to try ? Does anyone know if PCI-PCI bridges
> > $ have parameters for fifos ?
> > 
> > How about checking "Write posting enable".
> > If wirte posting is off,enable write posting enable.
> > 
> > This may help for your problem.
> 
> It might...
> 
> However I'll take a guess as to what is happening.....
> As soon as two interfaces are active you get two sets of
> concurrent read/write transfers on the slave (on board) pci
> bus.
> 
> I'd guess that these are not burst transfers, then the bridge
> will be doing separate transfers on the host pci bus for
> (almost) every byte/word transferred.
> 
> With only one interface active the bridge can merge the
> write (rx traffic) cyctes, and may be able to do burst
> reads to satisfy read (tx traffic).
> 
> I'd RTFM the ethernet chipset datasheet VERY closely and possibly
> look at transmitting/receiving into 32byte aligned buffers.
> (Which will almost certainly require a misaligned
> copy of the data by the cpu.)

Thanks, I'll try this. But I also get the problem when using only one of the
interfaces of the DFE580 (using an extra etherpowerII to act as router), so
it seems that the problem is when there is concurent activity on either
the primary or secondary PCI bus.

--
Manuel Bouyer, LIP6, Universite Paris VI.           Manuel.Bouyer@lip6.fr
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