> 
> $ Does anyone have an idea on what to try ? Does anyone know if PCI-PCI bridges
> $ have parameters for fifos ?
> 
> How about checking "Write posting enable".
> If wirte posting is off,enable write posting enable.
> 
> This may help for your problem.

It might...

However I'll take a guess as to what is happening.....
As soon as two interfaces are active you get two sets of
concurrent read/write transfers on the slave (on board) pci
bus.

I'd guess that these are not burst transfers, then the bridge
will be doing separate transfers on the host pci bus for
(almost) every byte/word transferred.

With only one interface active the bridge can merge the
write (rx traffic) cyctes, and may be able to do burst
reads to satisfy read (tx traffic).

I'd RTFM the ethernet chipset datasheet VERY closely and possibly
look at transmitting/receiving into 32byte aligned buffers.
(Which will almost certainly require a misaligned
copy of the data by the cpu.)

	David

-- 
David Laight: david@l8s.co.uk