In article <20011008214126.A15489@beverly.kleinbus.org>
is@netbsd.org wrote:

> > On siop (53c720/770/8x0) case, we have to support PCI siop (53c8x0)
> > on big endian machines (like macppc etc.),
> 
> yes - what do they do? or does it "just work" with the LE mode chip on the
> LE PCI bus and bus_space functions for PCI?

Yes, it just works.

When the chip is in LE mode, byte address is still same on
both LE and BE hosts. (i.e. lower bits are lower address.)
When BE hosts access to LE bus in u_int16_t or u_int32_t,
byteswapping is required, but it is handled by
bus_space(9) functions or bus bridges.
Explicit byteswap functions are required to pass
non-bytestream values via DMA by bus-master devices
which assume that their hosts are little-endian.
(where htole32()/le32toh() is used)

If the chip is in BE mode, we have to switch byte lane
on both LE and BE hosts, but the byte address is also
same on both LE and BE hosts (lower bits are higher address).
On word access to BE bus, bus_space(9) functions
(or bus bridges) should handle byte-swapping on LE hosts.
(But I guess there is no LE machines with BE bus)

Current siop supports only LE mode, but it works
on both BE and LE hosts.

Current osiop works with both LE and BE mode, but
it assumes endian mode of the chip is the same
with host's endian.

If we want to make the drivers support both LE and BE mode
on both LE and BE hosts, we have to add more endianness stuff..
---
Izumi Tsutsui
tsutsui@ceres.dti.ne.jp