>> [enough state to do a "may_i_tsleep()" call]

> Basically, it's a single instruction in the interrupt stub (increment
> interrupt nesting level) and another in the return (decrement),

On CISC architectures, perhaps (i386, vax, 68k).  SPARC, I can't see
how to get it down below four instructions (sethi, ld, add/sub, st),
and as I recall it, the PowerPC is similar.  On some such
architectures, there's also a classic race between the ld-add/sub-st
sequence and other interrupts occurring, a race which if it goes wrong
will corrupt the count; on the SPARC, ISTR something about double error
halts which would mean it's not an issue, but can't recall whether that
applies to interrupts or just traps.  If you have to splhigh() around
that, the instruction count goes up: rd, nop, nop, nop, or, wr, nop,
nop, nop, sethi, ld, add/sub, st, wr, nop, nop, nop.

Of course, that's still no more than 17 instructions, only two of which
access memory (which the SPARC, at least, hates to do).  The details
will vary on other architectures, of course, but even 34 instructions
and two four references (per interrupt, naturally) may end up being
judged worth it....

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