Subject: Re: Multiple busses of the same kind
To: None <thorpej@zembu.com>
From: Nathan J. Williams <nathanw@MIT.EDU>
List: tech-kern
Date: 07/31/2001 17:26:00
Jason R Thorpe <thorpej@zembu.com> writes:

> On Tue, Jul 31, 2001 at 04:55:41PM -0400, Todd Vierling wrote:
> 
>  > : On an Alpha with pci and pci-to-isa bridge?
>  > 
>  > ...and where is it mapped on the DNARD, too?
> 
> Who cares where it's mapped in the CPU's address space... if it's
> ISA, it has to be compatible with ISA devices, which means it has
> to conform to certain constraints.

We're failing to communicate... I think they read your comment a few
messages ago in this thread:

On Mon, Jul 30, 2001 at 12:23:41PM -0700, Jason R Thorpe wrote:
> On Mon, Jul 30, 2001 at 12:16:37PM -0700, Bill Studenmund wrote:
> 
>  > True, but then wouldn't both of these isa busses appear in different parts
>  > of the processor's address space?
>  > 
>  > Does our isa code deal with isa busses not being at 0-1 MB?
> 
> Um, that can't happen :-)

as referring to 0-1MB of the CPU address space, not 0-1MB of the PCI
address space.

        - Nathan