On Mon, 30 Jul 2001, Jason R Thorpe wrote:

> On Mon, Jul 30, 2001 at 12:16:37PM -0700, Bill Studenmund wrote:
>
>  > True, but then wouldn't both of these isa busses appear in different parts
>  > of the processor's address space?
>  >
>  > Does our isa code deal with isa busses not being at 0-1 MB?
>
> Um, that can't happen :-)

Why not? I admit it'd be weird for an i386, but can't that happen for
other architectures, and also wouldn't that have to happen if, as Nathan
was suggesting, we had multiple primary PCI busses, each with a
subtractive decode isa bus on it?

Yes, I agree it's a sick concept, and not something we should rush to
support. :-)

Take care,

Bill