On Tue, 10 Apr 2001, Thor Lancelot Simon wrote:
> > BTW, I see the performance drop with hbench too - the bandwidth
> > for 128KB transfer size is ~50% of 64KB one on my PIII.
> 
> I ran into an issue like this (oh, boy, did I ever!) with CRC-32 in
> one of my programs.  Doing a whole large buffer at once stomped on all
> the cache lines the CRC table (think, the kernel stack or whatever other
> might be in the D cache) and code itself (remember, the L2 cache is not
> split I/D) was in, causing cache thrashing as the data being worked on
> and the "other process state" fought for lines.  I bet paring things down
> to 64K or even smaller chunks done in a loop will in fact help.

Would something like "page coloring" help here? (Do we have that?)


 - Hubert

-- 
Hubert Feyrer <hubert.feyrer@informatik.fh-regensburg.de>