Subject: Re: DMA COHERENCY [ was Re: CVS commit: syssrc ]
To: Matthew Jacob <firstname.lastname@example.org>
From: Manuel Bouyer <email@example.com>
Date: 03/03/2001 21:20:05
On Thu, Mar 01, 2001 at 01:01:52PM -0800, Matthew Jacob wrote:
> > > Yes. It isn't just sparc- there are other architectures have this issue as
> > > well- alpha for example. But alpha has an instruction that can ensure
> > > coherency at bus_dmamap_sync time (mb).
> > This is between CPU and RAM, something that should be handled at
> > dmamem_map(BUS_DMA_COHERENT) time.
> I have reason to believe that in fact mb affects I/O device write buffers.
Ok, I don't know alpha that well :)
> > I prefer the fist. We may use memory not allocated from bus_dmamem_alloc()
> > BUS_DMA_COHERENT should be used with care, though, as this is not guaranteed
> > to work everywhere (I'm not sure a PCI device can be mapped coherent on
> > a mips CPU, for example).
> Should an error be returned if you cannot load with BUS_DMA_COHERENT?
Yes, for sure. On bus which are always BUS_DMA_COHERENT it would be
just ignored. This way, if the driver relies on this it can at last
abort the current operation.
Manuel Bouyer, LIP6, Universite Paris VI. Manuel.Bouyer@lip6.fr