Subject: Re: DMA COHERENCY [ was Re: CVS commit: syssrc ]
To: Manuel Bouyer <email@example.com>
From: Matthew Jacob <firstname.lastname@example.org>
Date: 03/01/2001 13:01:52
> > Yes. It isn't just sparc- there are other architectures have this issue as
> > well- alpha for example. But alpha has an instruction that can ensure
> > coherency at bus_dmamap_sync time (mb).
> This is between CPU and RAM, something that should be handled at
> dmamem_map(BUS_DMA_COHERENT) time.
I have reason to believe that in fact mb affects I/O device write buffers.
> I prefer the fist. We may use memory not allocated from bus_dmamem_alloc()
> BUS_DMA_COHERENT should be used with care, though, as this is not guaranteed
> to work everywhere (I'm not sure a PCI device can be mapped coherent on
> a mips CPU, for example).
Should an error be returned if you cannot load with BUS_DMA_COHERENT?