Subject: Re: ARM port organisation (was: Re: NetBSD/hpcarm snap code)
To: None <Richard.Earnshaw@arm.com>
From: Jason R Thorpe <email@example.com>
Date: 02/17/2001 09:21:14
On Sat, Feb 17, 2001 at 01:46:31PM +0000, Richard Earnshaw wrote:
> (fast context switch) extension in the MMU. If you are prepared to
> restrict (all?) processes to 32M of VM, then you can avoid cache flushes
> on a context switch; this also warrants a separate configuration.
Oh, yah, the WinCE hack -- I don't think we want to use that feature
on the FCS-capable chips.
-- Jason R. Thorpe <firstname.lastname@example.org>