>       If you are worried about NetBSD interrupt implementation on
> PowerPC, I would recommend that you ensure the interrupt handler code
> utilizes the PowerPC lwarx/stwcx. instructions.  I do not know if it
> already has been fixed, but the last versions that I saw were enabling and
> disabling the external interrupts bit in the MSR in do_pending_int() to
> atomically manipulate the pending interrupts mask instead of using the
> atomic load/store instructions.

Actually, I think it's even worse than that.  If I'm not mistaken, the prep,
bebox, and macppc ports each disable all external interrupts when running
any interrupt handler, whether immediately upon receipt or later in
do_pending_int().  This includes even software interrupt handlers.

If so, this seems overly cautious, and detrimental to interrupt latency. 
Could someone who knows the truth please comment?

Regards,

David Querbach
Real-Time Systems Inc.