>>>>> David Querbach writes:

David> Not yet, though I probably will, eventually.  Right now I'm trying to design
David> an interrupt handling mechanism to take advantage of the three levels of
David> interrupt controllers and 40 or 50 possible interrupt sources in an embedded
David> PowerPC system.

	If you are worried about NetBSD interrupt implementation on
PowerPC, I would recommend that you ensure the interrupt handler code
utilizes the PowerPC lwarx/stwcx. instructions.  I do not know if it
already has been fixed, but the last versions that I saw were enabling and
disabling the external interrupts bit in the MSR in do_pending_int() to
atomically manipulate the pending interrupts mask instead of using the
atomic load/store instructions.

David