> I believe the extremely lousy hardware in many serial controllers
> insists on avoiding almost any latency; thus its higher priority.
> 
> OTOH feeding the controller is a *very* short interrupt, so splhigh
> never suffers much latency from it. The expensive work is done at 
> spltty or splsoftserial (? probably; below splhigh anyway).

I wasn't concerned about the latency, but about mutual exclusion.  If serial
interrupts are always enabled, the serial handlers must be very careful how
they interact with even splhigh() code.
 
> Have you done any measurements on various ipl latencies? This could 
> be interesting.

Not yet, though I probably will, eventually.  Right now I'm trying to design
an interrupt handling mechanism to take advantage of the three levels of
interrupt controllers and 40 or 50 possible interrupt sources in an embedded
PowerPC system.

Regards,

David Querbach
Real-Time Systems Inc.