Subject: Re: MI I^2C drivers
To: Ben Harris <>
From: Castor Fu <>
List: tech-kern
Date: 07/26/2000 10:30:12
On Wed, 26 Jul 2000, Ben Harris wrote:

. . . 
> [ Prompted by pk's TOD clock interface, and the fact the clock Acorn
>   systems use attaches to an I^2C bus, so I want an MI I^2C infrastructure
>   for it. ]
> Currently, there seem to be at least three sets of infrastructure in the
> kernel for handling Philips' I^2C bus.  There's the MI stuff in
> sys/dev/i2c, and MD stuff in sys/arch/arm26/ioc/{iic,rtc}.c and
> sys/arch/arm32/dev/{iic,rtc}.c.  This is clearly silly.

But the stuff in sys/dev/i2c is just not that useful.  We wanted a more
general framework.  On our system we have something like the following:

	cai2c0  at chipa?
	iicbus* at cai2c?
	zot0 at iicbus? slaveaddr 0x34          # normalized slave address 
	bar0 at iicbus? slaveaddr 0x46          # normalized slave address
The iicbus device has an ioctl for servicing raw io requests through
the interface which is also used by child devices.  
The io requests at the read/write multiple bytes to support devices
like ours where the I2C interface can spit out multiple bytes at a time. 

Things get even more complicated if you want to support multiple
masters, but I don't know of any systems which take advantage of
that part of I2C.

I've heard rumors that cgd has similar requirements to ours. . . 

If people think this is of general interest we can start iterating on
a common framework.