Subject: Re: PCI power state code (was: CVS commit: syssrc)
To: John Hawkinson <jhawk@MIT.EDU>
From: Johan Danielsson <>
List: tech-kern
Date: 07/17/2000 20:54:59
John Hawkinson <jhawk@MIT.EDU> writes:

> It seems to me that the D3 state case is not quite right. You assert
> that IO and MEM are disabled, but that's merely what happens on your
> machine with your BIOS. Presumably that is not the case on all
> machines. I assume that "Most" BIOSes will move the device to D0 on
> their own and do the setup, they are not an issue. Some BIOSes may
> do the PCI BAR setup but leave the device in D3. For those cases, it
> should be adequate to move the device to D0 and things should just
> work (disclaimed: that's how it works for the i82559, for which the
> Sony VAIO bios has such a bug. I don't have a PCI PM spec and I'm
> not certain absolutely what is required to switch to D0).

    5.4   PCI Function D3 State
    All PCI functions must support D3.
    In this state, function context need not be maintained.  However,
    if PMEs are supported from D3, then PME context must be retained
    at a minimum.  When the function is brought back to D0 (the only
    legal state transition from D3), software will need to perform a
    full reinitialization of the function including its PCI
    Configuration Space.
    There is a minimum recovery time requirement of 10 ms (enforced by
    system software) between when a function is programmed from D3 to
    D0 and when the function is accessed (including PCI configuration
    accesses).  This allows time for the function to reset itself and
    bring itself to a power-on condition.  It is important to note
    that regardless of whether the function is transitioned to D0 from
    D3hot or D3cold, the end result from a software perspective is
    that the function will be in the D0 Uninitialized state.
    5.4.1   Software Accessible D3 (D3hot)
    Functions in D3hot must respond to configuration space accesses as
    long as power and clock are supplied so that they can be returned
    to D0 by software.
    When programmed to D0, the function performs the equivalent of a
    warm (soft) reset internally and returns to the D0 Uninitialized
    state without PCI RST# being asserted.  Other bus activity may be
    taking place during this time on the same PCI bus segment so the
    device that has returned to D0 Uninitialized state must ensure
    that all of its PCI signal drivers remain disabled for the
    duration of the D3hot to D0 Uninitialized state transition7.
    The only function context that must be retained in D3hot and
    through the soft reset transition to the D0 Uninitialized state is
    the PME context.
    5.4.2   Power Off (D3cold)
    If Vcc is removed from a PCI device, all of its PCI functions
    transition immediately to D3cold.  All PCI device functions
    support this state by default.  When power is restored, PCI RST#
    must be asserted and functions will return to D0 (D0 Uninitialized
    state) with a full PCI 2.1 compliant power-on reset sequence.
    Whenever the transition from D3 to D0 is initiated through
    assertion of PCI RST#, the power-on defaults will be restored to
    the function by hardware just as at initial power up.  The
    function must then be fully initialized and reconfigured by
    software after making the transition to the D0 uninitialized
    Functions that support PMEs from D3cold must preserve their PME
    context through the D3cold to D0 transition.  The power required
    to do this must be provided by some auxiliary power source
    assuming that no power is made available to the PCI device from
    the normal Vcc power plane.