Subject: Re: call for testing changes to le(4) for PCI on big-endian machine
To: None <email@example.com>
From: Izumi Tsutsui <firstname.lastname@example.org>
Date: 06/28/2000 09:05:11
> PR kern/9602 has changes for le(4) to make it work on a big-endian
> machine with a PCI front-end (it has worked for years on NetBSD/sparc
> on Sbus and obio, and sun3).
> We need someone who has the hardware (an le(4) ethernet board, and a
> big-endian machine with PCI (e.g. macppc, sparc64) to test the
> changes and let us know if they work, and therefore whether to commit
> or not.
(BTW, I believe Nonaka has a newer patch which changes only if_le_pci.c.)
The original LANCE chips (7990/79900) has "byte-swapping" support
for descriptors (LE_C3_BSWP in lancereg.h). sun3, sparc and
other big endian ports are using it.
But LE_C3_BSWP does not work properly for PCI frontend because
if_le_pci uses bus-master DMA transfer for passing descriptors.
According to the am79c970 manual, it does not seem the AMD assumes
79c97x will be used on big endian machines. (sigh)
Anyway, even though am79c97x chips are full functional
DMA transfer capable, current if_le_pci.c allocates
only one fixed transfer buffer (and it has only 16kbytes!).
All TX/RX packets are copied between the buffer and mbufs.
(i.e. it is just working on compatible mode with older LANCE.)
Furthermore, if_le_pci.c does not call bus_dmamap_sync(9) on DMA
operations. It would cause problems on non DMA cache coherent
if_le_pci.c should be re-written like other bus-master
DMA capable cards. dev/pci/if_sip.c seems good example.
(I have a plan for it, but it is not started yet ;-)