On Tue, Jun 20, 2000 at 02:02:34PM +0530, Vikram wrote:
> Hello Gurus,
>     I have some questions on DMA mapping.Pls. try to answer them at your
> best.
> The info I have is ( from man page of bus_dma) :
>     BUS_DMASYNC_PREREAD
>         Perform any pre-read DMA cache and/or bounce operations.
>     BUS_DMASYNC_POSTREAD
>         Perform any post-read DMA cache and/or bounce operations.
>     BUS_DMASYNC_PREWRITE
>         Perform any pre-write DMA cache and/or bounce operations.
>     BUS_DMASYNC_POSTWRITE
>         Perform any post-write DMA cache and/or bounce operations.
> Now can some one explain me

> 1) Whart is DMA cacheing?

Depending on machines there can be memory cache between the main memory
and CPU. If CPU change a byte, and it stay in cache and is not updated in main
memory you'll have to flush the cache before starting the DMA op (because the
device read from the main memory it would read incorrect data otherwise).
The same problem can happen the other way: the device writes data in main
memory but the cpu keep reading the cached data, to get the real value you
need to invalidate the cache before.

> 2) What are these bounce operations?

On some machines not all memory can be acceded from DMA devices (e.g.
memory > 16M from ISA bus, or memory > 4G from a 32bit PCI bus). So the
buffer may have to be copied in a 'DMA safe' memory before the device can
DMA it.


> 3) When it is used and it's advantages.

It's used when the hardware require it. From your driver you don't need to
deal with these low-level problems (this is where the bus_dma interface is
interesting), just do the BUS_DMASYNC when needed (that is BUS_DMASYNC_PREREAD
or BUS_DMASYNC_PREWRITE before starting a DMA operation, and
BUS_DMASYNC_POSTREAD/POSTWRITE once the DMA op is done).
These will probably be no-op on i386 (at last as long as xeons with more than
4G RAM are not supported). On an alpha or with more than 4G of RAM these ops
will probably copy the DMA buffer when needed (i.e. if it lives in a regions
> 4G). On a mips-based machine these ops will likely do cache
flush/invalidation. Remember that a PCI board doesn't run only on a PC, but
on any machine with a PCI bus ! If written properly your driver will run
on any of these machines without additionnal or machine-dependant code.

--
Manuel Bouyer, LIP6, Universite Paris VI.           Manuel.Bouyer@lip6.fr
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