Subject: Re: Structuring an MPC821/823/860 Port
To: None <firstname.lastname@example.org, email@example.com>
From: Wolfgang Solfrank <firstname.lastname@example.org>
Date: 03/30/2000 21:35:08
> The MPC821/823/860 chips are derived from the PowerPC, with two major
> 1. The MMU is more of a classical two-level page directory / page table
> system, rather than the segment register / hash table system of the PPC600
AFAIK, while there is some hardware support for a two-level page table
scheme, there is no real need to follow this, as the tlb is under complete
software control. I don't know enough about these chips to decide whether
it makes sense to ignore this support.
> 3. Put the new code into the existing sys/arch/powerpc directory, and use
> Makefile switches and conditional compiliation to choose the required
> code for a particular chip. Create a sys/arch/mbx8xx directory to house
> the board-specific code.
This is the correct way to do this. I'm currently on my way to integrate
the 403GCX port into the tree. It will use kernel config file options
to decide what parts of the sys/arch/powerpc directory to actually compile.
You should do something similar.
> A similar question also arises in lib/libc/arch due to the lack of hardware
> floating-point support in the MPC821/823/860 chips.
Same problem with the 403 here. While I intend to integrate an fpu
emulator based on sys/arch/m68k/fpe in the kernel (at least as an option),
it probably makes sense to also have the possibility to compile everything
without fpu instructions and use library routines to do the computation.
Whether to have two userlands, or just two libc, makes more sense, I'm not
really sure about. For the base distribution, just using a separate
libc should probably be enough. Some floating point intensive stuff
may be different kettle of fish.
BTW, anyone working on separating the MI parts out of sys/arch/m68k/fpe?
ws@TooLs.DE Wolfgang Solfrank, TooLs GmbH +49-228-985800