According to Martin Husemann:
>
>Either I misunderstood the original problem or this situation should be
>realy strange. If we were talking about i386 here, everyone would yell
>"broken PC hardware design".
>

Yeah - more than likely :-)

>Where cache hardware isn't able to cooperate with a foreign DMA master, it
>has to pay it's price by not caching the DMA target memory, IMHO.
>

Well, that is not the only solution.  You can pull tricks like
invalidating cache lines or flushing the entire cache.  The solution
you end up using really depends on how much of a performance hit you
are going to see.  This book:

UNIX Systems for Modern Architectures: Symmetric Multiprocesssing and Caching for Kernel Programmers 
    by Curt Schimmel 
    Addison-Wesley Pub Co; ISBN: 0201633388


Goes into great details about various approaches you can use to
maintain cache coherency when the processor does not do it for you.
It mentions the MIPS processor by name as being one where you have to
maintain the cache coherency yourself.

-- 
===============================================================================
Brett Lymn, Computer Systems Administrator, BAE SYSTEMS
===============================================================================