Subject: Re: bus_dma and cache line sizes
To: None <email@example.com>
From: Jason R Thorpe <firstname.lastname@example.org>
Date: 03/25/2000 12:03:17
On Fri, Mar 24, 2000 at 06:00:55PM -0800, Castor Fu wrote:
> The QED5231 processor has a 32-byte cache line size,
> and the tulip family uses a 16-byte (or more) descriptor.
[ snip ]
> The two obvious solutions are to access the descriptors
> as uncached memory, or I need to know the cache line size to
> pad the descriptors to 32 bytes. Any suggestions
> on what "The Right Thing" is?
Wow, that's Cool.
So, those descriptors are being mapped with BUS_DMA_COHERENT. On e.g.
the PMAX port, COHERENT regions are mapped uncached. This is partially
to avoid doing cache flushes that might be more expensive than just doing
the uncached access.
Looks like it would avoid this problem, too.
I haven't seen the bus_dma implementation for your platform, but I would
suggest doing the same thing in the COHERENT case as the PMAX port does.
We could also pad out to the cacheline size that's in the PCI configuration
header, but that isn't always accurate on some platforms, and isn't always
necessary (e.g. this problem doesn't affect the Alpha because the caches
themselves are coherent).
-- Jason R. Thorpe <email@example.com>