Subject: Re: bus_dma and cache line sizes
To: Nathan J. Williams <nathanw@MIT.EDU>
From: Warner Losh <>
List: tech-kern
Date: 03/25/2000 01:20:40
In message <> Nathan J. Williams writes:
: Isn't it usually the responsibility of the cache and memory
: controllers to keep the cache coherent with memory in the presence of
: DMA (or multiprocessing)? Why isn't that happening here?

Because MIPS architecture moves all of that stuff into software to
reduce gate count. :-)

The problem is easy to work around for most applications (make sure
that you only use one cache line's worth of data at a time and make
sure that the device doesn't dma into the middle of data that you are
about to write).  NetBSD's busdma doesn't have an api for getting the
cache line size for a given bus dam tag, so the driver can't do the
optimal thing and just use 2x the memory for these 16 byte messages
to/from the card.

I'd expect that the boundary parameter to bus_dmamap_create should be
32 in this case, but I don't see how the driver can find this out.  It
is late and maybe I'm missing something.